Sanyo DC-TS960WL, Руководство по обслуживанию

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IC BLOCK DIAGRAM & DESCRIPTION
IC831,T436416A-SF(DRAM)
38
CLK
37
CKE
19
CS
18
RAS
17
CAS
16
WE L(U)DQM
20,21
15,39
38 CLK
22~26,
29~35
ADD
2,4,5,7,8,10,
11,13,42,44,
45,47,48,50,
51,53
DQI
15 LDQM
LWE
BA0,BA1
Programming Register
Timing Register
LRAS LCBR LWE LDQM
Latency & Burst Length
Column Decode
Data Input Register
Col. Buf
fer
Row Decoder Output Buf
fer
I/O Control
Sense AMP
IM x 16
IM x 16
IM x 16
IM x 16
Row Buf
feer
Refresh Counter
Address Register
LRAS
LCBR
Bank Select
INPUT FUNCTION
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enadling all input.
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE shouid be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same oins.
Row address : RA0~RA11,column address : CA0~CA7
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS,WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output
Mask
Data Input/Output
Power Supply/Ground
Data Output
Power/Ground
No
Connection/Reserved
for Future Use
PIN
CLK
CS
CKE
A0 ~ A11
BA0 ~ BA1
RAS
CAS
WE
L(U)DQM
DQ0 ~ DQ15
V
DD
~ V
SS
V
DDQ
/V
SSQ
N.C/REU
PIN DESCRIPTION
LCAS LWCBR