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IC BLOCK DIAGRAM & DESCRIPTION
IC500 M21L216128A-10T(SRAM)
39
6
40
41
17
A0-A16
1-5,
18-22,
24-27,
42-44
DQ1-DQ8
17-10,
13-16
DQ9-DQ16
29-32,
35-38
GND
12,34
VCC
11,33
Description
PAddress Input
Chip Enable Inpu
Data Input / Output
Write Enable Inout
Lower Byte Enable Input (DQ1 to DQ8)
Higher Byte Enable Input (DQ9 to DQ16)
Output Enable Input
Power
Ground
No Connection
Pin No.
1 - 5, 18 - 22
24 - 27,4 2 - 44
6
7 - 10, 13 - 16
29 - 32, 35 - 38
17
39
40
41
11, 33
12, 34
23, 28
Pin Descriptions
CE
OE
HB
LB
WE
Symbol
A0 - A16
CE
DQ1 - DQ16
WE
LB
HB
OE
VCC
GND
NC
Decoder
512 x 4096
Memory
Array
Input
Data
Circuit
Column I/O
Input
Data
Circuit
Control
Circuit
3
1
2
Control
part
GND
DC INPUT:Vin
DC OUTPUT :Vo
IC900 PQ033ES1MXP(Regulator)