SanDisk SDMB-16, Руководство по эксплуатации продукта

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MultiMediaCard Product Manual
SanDisk MultiMediaCard Product Manual Rev. 2 © 2000 SANDISK CORPORATION 64
6.1.6 Read CID/CSD Registers
Unlike the MultiMediaCard protocol (where the
register contents are sent as a command response),
reading the contents of the CSD and CID registers
in SPI mode is a simple read-block transaction.
The card will respond with a standard response
token followed by a data block of 16 bytes suffixed
with a 16 bit CRC.
6.1.7 Reset Sequence
The MultiMediaCard requires a defined reset
sequence. After power on reset or CMD0 (software
reset) the card enters an idle state. Note that a t
least 74 clock cycles are required prior to starting
bus communication. At this state the only legal
host command is CMD1 (SEND_OP_COND). In
SPI mode, however, CMD1 has no operands.
The host must poll the card (by repeatedly
sending CMD1) until the ‘in-idle-state’ bit in the
card response indicates (by being set to 0) that the
card completed its initialization processes and is
ready for the next command.
6.1.8 Clock Control
The SPI bus clock signal can be used by the SPI
host to set the cards to energy saving mode or to
control the data flow (to avoid under-run or over-
run conditions) on the bus. The host is allowed to
change the clock frequency or shut it down.
There are a few restrictions the SPI host must
follow:
• The bus frequency can be changed at any
time (under the restrictions of maximum
data transfer frequency, defined by the
MultiMediaCards).
• It is an obvious requirement that the clock
must be running for the MultiMediaCard
to output data or response tokens. After
the last SPI bus transaction, the host is
required to provide 8 (eight) clock cycles
for the card to complete the operation
before shutting down
the clock.
Throughout this 8 clock period, the state
of the CS signal is irrelevant. It can be
asserted or deasserted. Following is a list
of the various SPI bus transactions:
• A command/response sequence. Eight
clocks after the card response end bit.
The CS signal can be asserted or
deasserted during these 8 clocks.
• A read data transaction. Eight clocks
after the end bit of the last data
block.
• A write data transaction. Eight clocks
after the CRC status token.
• The host is allowed to shut down the clock
of a “busy” card. The MultiMediaCard
will complete the programming operation
regardless of the host clock. However, the
host must provide a clock edge for the card
to turn off its busy signal. Without a clock
edge,
the MultiMediaCard (unless
previously disconnected by deasserting
the CS signal) will force the dataOut line
down, permanently.
6.1.9 Error Conditions
6.1.9.1 CRC and Illegal Command
All commands are optionally protected by CRC
(cyclic redundancy check) bits. If the addressed
MultiMediaCard’s
CRC check fails, the
COM_CRC_ERROR bit will be set in the card’s
response. Similarly, if an illegal command has
been received, the ILLEGAL_COMMAND bit will
be set in the card’s response.
There are different kinds of illegal commands:
• Commands which belong to classes not
supported by the MultiMediaCard (e.g.
interrupt and I/O commands).
• Commands not allowed in SPI mode (e.g.
CMD20 – write stream).
• Commands which are not defined (e.g.
CMD6).
6.1.9.2 Read, Write and Time-out Conditions
The times that a time-out condition for
read/write/erase operations occur are (card
independent) 10 times longer than the typical
access/program times for these operations given