SanDisk SDMB-16, Руководство по эксплуатации продукта

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MultiMediaCard Product Manual
SanDisk MultiMediaCard Product Manual Rev. 2 © 2000 SANDISK CORPORATION 56
5.10 Timings
All timing diagrams use the following schematics and abbreviations:
Table 5-11 Timing Diagram Symbols
S Start Bit (= 0)
T Transmitter Bit (Host = 1, Card = 0)
P One-cycle Pull-up (= 1)
E End Bit (=1)
Z High Impedance State (-> = 1)
D Data Bits
* Repeater
CRC Cyclic Redundancy Check Bits (7 Bits)
Card Active
Host Active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up
resistors R
CMD
respectively R
DAT
. Actively-driven P-bits are less sensitive to noise superposition.
All timing values are defined in Table 5-12.
5.10.1 Command and Response
Both host command and card response are clocked out with the rising edge of the host clock. The
minimum delay between the host command and card response is N
CR
clock cycles. This timing diagram is
relevant for host command CMD3.
<---- Host Command ----> <-NCR Cycles-> <-------- Response --------->
CMD S T Content CRC E Z
* * * * * *
Z S T Content CRC E Z Z Z
Figure 5-5 Command Response Timing (Identification Mode)
There is just one Z bit period followed by P bits pushed up by the responding card. This timing diagram
is relevant for all responded host commands except CMD1,2,3.
<---- Host Command ---->
<-N
CR
Cycles->
<-------- Response --------->
CMD S T Content CRC E Z Z P
* * *
P S T Content CRC E Z Z Z
Figure 5-6 Command Response Timing (Data Transfer Mode)