Samsung STH-A225, Руководство по обслуживанию

Страница: 48 / 49

STH-A225 Circuit Description & Circuit Diagrams
SAMSUNG Proprietary-Contents may change without notice
10-10
U215(201,205)
C244(212,213,214)
CN201
Q207
2012
NOTE: WAITING FOR REPLAY FROM SAMSUNG ABOUT C_F PIN
NOTE: TDMA EVENT -SPARE TIMMING SIGNALS STH-A221_BASE
D205
R282(204,277)
ZD207
1UF
TP222
1
RESERVED0
2
RESERVED1
RI
16
20
RTS
7
RX_AUDIO
11
TX_AUDIO
8
GND1
GND2
10
12
GND3
19
GND4
GND5
25
23
CTS
9
C/F1
26
C/F2
13
DP_RX_DATA
DP_TX_DATA
14
3
DSR
24
DTR
CN201
17
CD
6.3V
2.2UF
C237
1
2
3 4
5
C238
NC
ZD202
100NF
C211
ZD207
0
R264
100NF
C218
D202
C231
1NF
IVCC
22
U204
R229
R262
NC
R231
WBDTX
XIN
F1
E1
XOUT
VBAT
3.3K
TX_SYNC
UBE
T15
VALID_STRB
J1
VCTCXO
F3
E2
VCTCXO_GND
F4
VCTCXO_PC
VCTCXO_VDD F2
WBDRX
G1
G2
TEST1 TEST2
C4 A3
TEST3
TESTER_MODE
B3
TX_BA
T
J2
TX_CLK
K2 K4
TX_DA
T
A_1
TX_DA
T
A_2
K3 K1
SRAM_CS
STROB0
B8 C8
STROB1 STROB2
C10 D10
STROB3
K14
TBREAKPT
G15
TDMA_EVENT_1 TDMA_EVENT_2
G16
B4
SEN2
SI2
N2
SIN_1
M16
T11
SIN_2
SLOT_T
D1
1
P2
SO2
L16
SOUT_1
SOUT_2
T10
P16
RI_N R
T
S_N
T6
H13
RX_BA
T
L4
RX_CLK
RX_DATA
L2
L3
RX_SYNC
SCK2
N1
D9
SCLK
N3
POWER_HOLD
PREAMP_G
J16
PWM_0
D13
A9
PWM_1 PWM_2
B9 C9
PWM_3
RESET
A2
J15
RF_BAND
T3
PDM_1_N
D1 E4
PDM_1_P PLL_CLK
K15 K16
PLL_DA
T
A
PLL_STRB_1
J13 J14
PLL_STRB_2
POWER_FAIL
C2
C3
MODE_STS
NOPC
B12 C1
1
NR
W
A1
OSC_32K_GND
A6
P0 P1
D7
H16
P
A_GA
T
E
D3
PDM_0_N PDM_0_P
D2
IVDD4
LOCK_DET
G14
A1
1
MAS0 MAS1
B1
1
MCLK
A12
M15
MEM8/16
T14
MEMOEB
MEMWEB
T13
M2
F13 GP_OUT
H3 IFIC_RESET
T7
IRDA_RXD IRDA_TXD
T9
IVDD1
R1
R16
IVDD2
IVDD3
A7
C7
D15
GPIO_0_8 GPIO_0_9
D16 A14
GPIO_1_0 GPIO_1_1
B14 C14
GPIO_1_2 GPIO_1_3
A13 B13
GPIO_1_4 GPIO_1_5
C13 A15
GPIO_0_14 GPIO_0_15
B15 F16
GPIO_0_2 GPIO_0_3
E13 E14
GPIO_0_4 GPIO_0_5
E15 E16
GPIO_0_6 GPIO_0_7
D14
FBURST
FLASH_CS
N16
FSYNC
M1
F14
GPIO_0_0 GPIO_0_1
F15 C15
GPIO_0_10 GPIO_0_1
1
C16 B16
GPIO_0_12 GPIO_0_13
A16
D_OUT
D4
EDD1
EDD2
J4
R8
EDD3
EDD4
H15
D12
EDD5
B6
EX_TX_CLK
EX_TX_DA
T
A
C6
A10
C12
DGND6
DGND7
D8
B7 DGND8
DSR_N
T2 T5
DTR_N D_IF_OUT
H4
D_IN
B10
A8
D7
D8
P13
R14
D9
DCD_N
T4
DGND1
H1
P1
DGND2
DGND3
T8
T16
DGND4
DGND5
H14
D13
D14
N14
N15
D15
D2
P11
N11
D3
D4
R12
P12
D5
D6
N12
R13
CS_RES1
CS_RES2
M14
T1
CTS_N
D0
N10
R11
D1
D10
R15
P14
D11
D12
P15
N13
A5
BB_TICE
D5
BB_TMS
J3
BIN
T12
BOOT_MODE
BVDD
C1
CLK_SEL_0
G4
G3
CLK_SEL_1
M13
ARM_TMS
AUX_CLK
L1
AUX_DA
T
A
M3 M4
AUX_STRB
BBCLK
H2
BB_JT
AG_RESET
A4
BB_TCK
B5 C5
BB_TDI
BB_TDO
D6
A7
A8
P5
R6
A9
AGND
E3
ALC_EN
G13
ARM_TCK
K13
ARM_TDI
L15 L14
ARM_TDO
L13
A19
A2
R3
A20
R10
P10
A21
N4
A3
A4
P4
R4
A5
A6
R5
N5
A11
A12
R7
P7
A13
A14
N7
P8
A15
A16
N8
R9
A17
A18
P9
N9
U203
32K_XIN
B2
B1
32K_XOUT
A0
R2
P3
A1
A10
P6
N6
4.7K
R214
VCC
U311
1 2 5 6
3
G
4
6.3V
S-VCC
D3
S-VSS
B8 S-WE#
VPP
E4
C229
10UF
NC7
NC8
H3
H10
NC9
S-CS1# G10
D8 S-CS2
F3 S-LB#
F5 S-OE#
S-UB# F4
D9
NC1
NC10
H11
H12
NC11
NC2
A2
A11
NC3
NC4
A12
C4
NC5
NC6
H1
H2
F-OE#
F-RP# D4
D10
F-VCC
A10
F-VCCQ
H8
F-VSS
F-VSS
A9
C3
F-WE#
E3
F-WP#
A1
C9
DQ4
DQ5
C10
C8
DQ6
DQ7
B10
F8
DQ8
DQ9
F7
H7 F-CE#
H9
E8
DQ10
DQ11
E6
D7
DQ12
DQ13
C7
B9
DQ14
DQ15
B7
E9
DQ2
DQ3
E10
H5 A4
A5 H4
G6
A6
A7 G5
B4 A8
A9 B6
F9
DQ0
DQ1
F10
A14
A15 A5
B3 A16
A17 G4
G3 A18
A19 E5
G8
A2
A20 A3
A3 G7
H6 A0
A1 G9
B5 A10
A11 A4
A8 A12
A13 A7
A6
VCC
U206
7
CE1
CE2
6
5
CE3 GND
4
VDD
8
VOUT1
1
2
VOUT2
VOUT3
3
U212
100K
R243
R268 100
47K
R208
10NF
C242
22
R240
330K
2
3
1
R227
R261
22K
Q203
R273
100K
C222
10UF
6.3V
R275
100K
15PF
C203
C223
R218 22
VCC
VBAT
10K
R281
R228
270K
R207
22
D204
C217
NC
RX
TX
100K
R254
HP_PWR
C216
NC
R224
R246
VCC
22
6.3V
100K
C206
C235
33UF
R248
100NF
R241
NC
R253
0
D203
22K
ZD205
G2
S1
1
4
S2
U213
D1
6
3 D2
2 G1 5
100
R278
R210
0
10
R258
R272
NC
VCC
VCC
C244
NC
C202
100PF
C201
100PF
R266 100
C219
100NF
5
1 S1
S2 4
VCC
U209
6
D1
D2
3
G1
2
G2
0 R282
6.3V
C243 C239
33UF
6.3V
33UF
2.2UF
C228
6.3V
3
2
C220
2.2UF
6.3V
Q201
1
R236
390K
R217
22
C227
2.2UF
6.3V
VCC
R201
NC
100K
R250
22 R219
U210
ADJ
4
3
EN
GND
2
IN
1
OUT
5
BVDD
R251
100K
100K
R242
VCC
R269 100
VCC2
3
5
_RESET
100K
R232
U214
GND
2
1
SRT
4
VCC1
R203
1M
R225 22
100 R267
1
2
3
45
6
U208
10
R235
R247
6.8K
100K
R209
R260
1K
Q205
1
3
2
1UF
C224
1UF
C210
VCC
VCC
VCC
NC
C215
C226
10K
R213
VBAT
6.3V
10UF
C205
100NF
100 R265
D205
NC
R263
BOOT
C209
100NF
R249
100K
3 CONT
GND
2
1
VIN
5
VOUT
IVCC
BVDD
U215
BYP 4
470PF
C225
1K
1
2
3 4
5
R252
22
ZD203
R221
R244
100K
22PF
C241
47K
R239
R223
22
100NF
C233
C208
100NF
22 R226
20K
R255
100NF
C232
R211
C207
100NF
VBAT
100
0
R280
R216
R234
100K
1 2
3
4.7K
R256
ZD201
R212
NC
330K,1%
7
6
CE2
CE3
5 4
GND
8
VDD
1
VOUT1
VOUT2
2
3
VOUT3
U207
CE1
6.3V
ZD206
C236
2.2UF
BATT
GND
15PF
C204
R215
4.7K
0
R202
R257
2
3
1
NC
Q202
22 R222
22 R220
R238
330K,1%
100 R271
R276
100K
R206
10
C230
100NF
SI1305DL
Q206
D 3
G
1
S 2
10K
R274
VCC
6.3V
10UF
C221
6
D1
D2
3
G1 2 G2 5
1 S1
S2
4
U211
R233
U202
FC-255
R237
100K
ZD204
1
2
3 4
5
NC
3
1
VCC
Q204
2
VCC
100K
R245
1.2K
R259
100K
VBAT
R230
22 R279
BATT
R270 100
6.3V
2.2UF
C234
100NF
C240
BATT
BATT
RESET
SI2
C_FNSTRB
GBOOT_DI
BATT
HP_PWR
SIN2
SOUT2
V_RF3
V_RF1
VRX
AUX_ON
GBOOT_DI
DP_RX_DATA
DSR
SIN2
SCAN(7)
GBOOT_DI
RESET
SIN2
DO
SOUT2
RAPID
RX_CLK
VCTCXO_IN
STROB1
PDM_0_N
PA_GATE
V_F
SCLK
REED_SW
HP_PWR
DP_RX_DA
T
A
RESET
C_FNSTRB
SCLK
DO
C_FNSTRB
FLASH_CS
RTS
SRAM_CS
CTS
DTR
UBE
ADD(0)
FLASH_WP
V_F
RI
DP_TX_DATA MEMOEB
CD HP_PWR
MEMWEB
ADD(11) DATA(7)_T
ADD(10) DATA(6)_T
RX_AUDIO
ADD(9) DATA(5)_T
ADD(8) DATA(4)_T
SOUT2 CTS
ADD(7) DATA(3)_T
ADD(6) DATA(2)_T
ADD(5) DATA(1)_T
ADD(3:21)
ADD(4) DATA(0)_T
TX_AUDIO
DP_RX_DATA
ADD(3)
DP_TX_DATA
ADD(2)_T
HP_PWR
ADD(1)
RI
CD
LED_ON
ADD(21)
ADD(20) HP_PWR
ADD(19) DATA(15)
ADD(18) DATA(14)
ON_SW_SENSE
ADD(17) DATA(13)
ADD(16) DATA(12)
GBOOT_DI
ON_SW
ADD(15) DATA(11)
ADD(14) DATA(10)
DSR
ADD(13) DATA(9)
DATA(8:15)
ADD(12) DATA(8)
RTS
DTR
TX_SYNC
TX_DA
T
A
1
AUX_CLK
AUX_STRB AUX_DA
T
A
V_DET
DATA(6)_T DATA(6)
RF_BAND_PCS RF_BAND
DATA(5)_T DATA(5)
DATA(4)_T
DATA(4)
DATA(3)_T
DATA(3)
DATA(2)_T
DATA(2)
PDM
DATA(1)_T
DATA(1)
PLL_ON
DATA(0)_T DATA(0)
ADD(2)_T ADD(2)
EL_EN
POWER_HOLD
V_IF_VCO
V_DRV_PCS
RAPID
DATA(7)_T DATA(7)
DP_TX_DA
T
A
RT
S
DTR
CD
RI
DSR
CTS
V_F_EN
FLASH_WP
STRB0
DO
GBOOT_DI
SCLK
D_IF_OUT
LOCK_DET
ANALOG_DIG
ALC_EN
P
A_GA
T
E
TX_BA
T
RX_BA
T
PREAMP_G
RF_BAND PLL_CLK
PLL_STRB1
PLL_DA
T
A
TX_CLK
ADD(12)
ADD(11)
ADD(10)
ADD(9)
ADD(8)
ADD(7)
ADD(6)
IFIC_RESET
ADD(5)
BBCLK
V_RF2
ADD(4)
MODE_STS
ADD(3)
VALID_STRB PON_TX
ADD(2) BIN
ADD(0:21)
ADD(1)
WBDRX TX_BAT
ADD(0) WBDTX
SIN2 RX_DATA V_DRV_CELL IF_ON
SOUT2 RX_SYNC
VCTCXO_PC
V_PA_BIAS_PCS
DATA(11)
DATA(10)
V_PA_BIAS_CELL
DATA(9)
DATA(8) POWER_HOLD
DATA(7)
DATA(6)
DATA(5)
DATA(4) RF_BAND RF_BAND_PCS TX_PWR
DATA(3)
DATA(2)
DATA(0:15)
DATA(1)
DATA(0)
ADD(21) PDM
ADD(20)
ADD(19)
ADD(18)
ADD(17)
ADD(16)
ADD(15)
ADD(14)
ADD(13)
SCAN(4)
SCAN(5)
SCAN(6)
KEY(0) KEY(1) KEY(2) SVC_LED_ON AL
T_LED_ON
PON_VRF3 PON_LD PON_TX SEND_END IF_ON ON_SW_SENSE
DISPLAY_CS SO2
SRAM_CS SCK
FLASH_CS SEN
FSYNC
UBE
MEMOEB
MEMWEB
DATA(15)
DATA(14)
DATA(13)
DATA(12)
V_LNA_DIG
RX_BAT
PREAMP_G
V_LNA_ANALOG
PLL_ON
ANALOG_DIG
ANALOG_DIG
PON_VRF3
LNA_VCC
TX_RFBAND VIBRA
T
O
R
MIC_BIAS_EN AMP_EN HS_SENSE ARM_TDI ARM_TDO ARM_TMS ARM_TCK ARM_TBRK SLOT_T
SCAN(0) SCAN(1) SCAN(2) SCAN(3)
4. BASE Circuit Diagram