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Samsung KS57C0302, Руководство пользователя

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KS57C0302

USER'S MANUAL ERRATA

JUNE 1998

6. COMPARATOR (Page 12-2)

P1.0/CIN0/KS0

P1.1/CIN1/KS1

INTERNAL BUS

VREF

(EXTERNAL)

M

U

X

M

U

X

COMPARISON

RESULT

REGISTER
(CMPREG)

M

U

X

CMOD.7

CMOD.6

CMOD.5

0

CMOD.3

CMOD.2

CMOD.1

CMOD.0

4

8

REF
(INTERNAL) 

+

-

V

DD

1/2R

R

R

1/2R

NOTES:

1.     INT occures only for digital input selecting: for analog input, any INT doesn’t.
2.    The comparison results of CIN0, CIN1, CIN2, and CIN3 are respectively stored in 
       CMPREG.0, CMPREG.1, CMPREG.2, and CMPREG.3.

P1.2/CIN2/KS2

P1.3/CIN3/KS3

Figure 12-1. Comparator Circuit Diagram

Содержание KS57C0302

Страница 1: ...UAL ERRATA This document contains the corrections of errors typos and omissions in the following document Samsung 4 bit CMOS KS57C0302 Microcontroller User s Manual Document Number 20 57 0302 Publication May 1995 ...

Страница 2: ...rol Bits 0 0 0 Input clock frequency Interrupt interval time fx 212 1 02 kHz 220 fx 250 ms 0 1 1 Input clock frequency Interrupt interval time fx 29 8 18 kHz 217 fx 31 3 ms 1 0 1 Input clock frequency Interrupt interval time fx 27 32 7 kHz 215 fx 7 82 ms 1 1 1 Input clock frequency Interrupt interval time fx 25 131 kHz 213 fx 1 95 ms 2 MEMORY MAP Page 4 9 CMOD Comparator Mode Register FD7H FD6H 6 ...

Страница 3: ...c timer operates with IRQB set at each reference interval Serial I O interface Operates only if external SCK input is selected as the serial I O clock Operates if a clock other than the CPU clock is selected as the serial I O clock Timer counter 0 Operates only if TCL0 is selected as the counter clock Timer counter 0 operates Comparator Comparator operation is stopped Comparator operates Watch tim...

Страница 4: ... 250 ms 0 1 1 fx 29 8 18 kHz 217 fx 31 3 ms 1 0 1 fx 27 32 7 kHz 215 fx 7 82 ms 1 1 1 fx 25 131 kHz 213 fx 1 95 ms NOTES 1 Clock frequencies and stabilization intervals assume a system oscillator clock frequency fx of 4 19 MHz 2 Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released 3 The standard stabilization time for system clock os...

Страница 5: ...G M U X CMOD 7 CMOD 6 CMOD 5 0 CMOD 3 CMOD 2 CMOD 1 CMOD 0 4 8 REF INTERNAL VDD 1 2R R R 1 2R NOTES 1 INT occures only for digital input selecting for analog input any INT doesn t 2 The comparison results of CIN0 CIN1 CIN2 and CIN3 are respectively stored in CMPREG 0 CMPREG 1 CMPREG 2 and CMPREG 3 P1 2 CIN2 KS2 P1 3 CIN3 KS3 Figure 12 1 Comparator Circuit Diagram ...

Страница 6: ...me 8 x 2 fx 244 4 us 4 19MHz 1 Comparator operation enable 0 Comparator operation disable FD6H FD7H CMOD 7 CMOD 6 CMOD 5 0 CMOD 3 CMOD 2 CMOD 1 CMOD 0 4 7 VREF Figure 12 2 Comparator Mode Register CMOD Organization 8 COMPARATOR Page 12 4 ANALOG INPUT VOLTAGE CIN0 3 COMPARISON RESULT CMPREG REFERENCE VOLTAGE VREF COMPARATOR CLOCK CMPCLK fx 16 fx 128 COMPARISON START 0 UNKNOWN COMPARISON END COMPARI...

Страница 7: ... converts the analog voltage input at the CIN0 CIN3 pins into 4 bit digital code BITR EMB LD A 0FH LD P1MOD A Analog input selection CIN0 CIN3 LD EA 0CXH x 0 F comparator enable Internal reference conversion time 30 5 us at 4 19 MHz LD CMOD EA WAIT0 LD L 1H WAIT1 LD W A LD A 0H WAIT2 INCS A JR WAIT2 LD A CMPREG Read the result DECS L JR WAIT1 CPSE A W JR WAIT0 LD P2 A Output the result from port 2...

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