Circuit Descriptions
Samsung Electronics
6-17
6-6-2 NTSC/PAL Digital Encoder (VIC50 : SAA7128)
VIC50 inputted from pin4 with 27MHz generates HSYNC and VSYNC which are based on video signal. Each
HSYNC and VSYNC outputted from Pin8 and Pin7 are inputted to Pin157 and Pin158 of A/V decoder VIC1(ZIVA-
3). VIC1 is the synchronous signals with the video signal and control the output timing of 8bit video signal of ITU-
R601 format. (Pin180, 182, 184 ~ 189 (MSP))
8bit data is inputted to Pin9(MSB) and Pin16 of VIC50 and the inputted data is demuxed with each 8bit of Y/R-Y/B-
Y. The separate signal is encoded to NTSC or PAL by control of MIC1. The above signals, that is CVBS
(Composite Video Burst Synchronized)(Pin30), S-Video (Y:Pin27, C:Pin24), Y/Pb/Pr(Pin27/Pin29/Pin23) and
GB(Pin26/Pin29/Pin23). In course of encoding, 8bit data can extend to 10bit or more. To convert the extended data
to quantization noise as possible, VIC50 adopts 10bit D/A converter. VIC50 perform video en-coding as well as
copy protection.
VDATA
[7:0]
VSYNC
HSYNC
27M
MRST
SDA
SCL
9~16
7
8
4
40
42
41
Demultiplexer
Y
CR-CB
RGB encoding
Luminace
processing
MACROVISION
7.0.1/6.1
Cloed captions
CGMS
Chrominance
processor
CTRL+CFG
register
Trap
10-bit DAC
30
27
24
23
26
29
CVBS
Y
C
Cr/R
G
Cb/B
VIC1 (SSA7128)
Fig. 6-22
6-6-3 Amplifier (VIC51, VIC52 : BA7660)
VIC51 and VIC52 are 6dB amplifier. Based on CVBS signal, the final output level must be 2Vpp without 75ohm ter-
minal resistance. Because the level of video encoder output is only 1.1Vpp, the level is adjusted with the special
amplifier. When mute of pin1 is high active, if the pin is floating and connected to power, the output signal is never
outputted. CVBS, Y, C, Cr and Cb outputted from video encoder are inputted to VIC52 (Pin7, Pin2 and Pin4) and
VIC51 (Pin7 and Pin4) respectively and outputted from VIC52 (Pin10, Pin15 and Pin13) and VIC51 (Pin10 and Pin
13). Pin9, Pin12 and Pin14 of VIC51 and VIC52 are feedback pin to SAG compensation(DC characteristic compen-
sation of signal). Resistance(VR3-VR14) which is inserted to input terminal is bias resistance for input offset. The
signal to which gain is adjusted by amplifier is outputted from jack via 75ohm.
Содержание DVD-739
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Страница 90: ...PCB Diagrams Samsung Electronics 11 3 11 2 Jack ...
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Страница 92: ...Samsung Electronics 12 1 12 Wiring Diagram JACK PCB MAIN PCB DECK PCB PLAY PCB POWER PCB ...
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Страница 95: ...Schematic Diagrams 13 2 Samsung Electronics 13 1 S M P S ...
Страница 96: ...Schematic Diagrams Samsung Electronics 13 3 13 2 Main Power Supply ...
Страница 97: ...Schematic Diagrams 13 4 Samsung Electronics 13 3 Main Micom ...
Страница 98: ...Schematic Diagrams Samsung Electronics 13 5 13 4 Servo ...
Страница 99: ...Schematic Diagrams 13 6 Samsung Electronics 13 5 Video Y Output C Output CVBS Output ...
Страница 100: ...Schematic Diagrams Samsung Electronics 13 7 13 6 Audio ...
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Страница 104: ...Schematic Diagrams Samsung Electronics 13 11 13 10 DSP ...
Страница 105: ...Schematic Diagrams 13 12 Samsung Electronics CN18 TO KARAOKE KCN3 CN15 TO KEY CON21 13 11 Front Micom VFD Display ...
Страница 107: ...Schematic Diagrams 13 14 Samsung Electronics 13 13 Mute ...
Страница 108: ...Schematic Diagrams Samsung Electronics 13 15 13 14 Karaoke Power ...
Страница 109: ...Schematic Diagrams 13 16 Samsung Electronics 13 15 Play ...
Страница 110: ...Schematic Diagrams Samsung Electronics 13 17 13 16 Deck ...
Страница 111: ...Schematic Diagrams 13 18 Samsung Electronics 13 17 Remote Control ...