PJDK71351-03
MK71351
11/24
●
RF Characteristics
(Ta=25
℃
)
Item
Symbol
Condition
Min.
Standard
Max.
Unit
Transmitter
Maximum transmitter
power
POUT
0 dBm setting value
–
0
–
dBm
Center frequency
tolerance
FCERR
Master Clock tolerance <
40 ppm
-40
0
40
ppm
Modulation data rate
DRATE
–
–
1
–
Mbps
Modulation index
FIDX
–
0.45
0.50
0.55
–
Bandwidth Time
BT
GFSK
–
0.5
–
–
Receiver
Receiver sensitivity
PSENS
PER = 30.8 % (*1)
–
-93.5
-
dBm
Maximum receiving
Power
PRXMAX
PER = 30.8 % (*1)
–
–
-10
dBm
(*) Condition: VBAT=VDDIO=3.0V, GND=0V
(*1) PER=30.8 % corresponds to BER=0.1 %.
●
Power Supply Sequence
VBAT
VDDIO
Master Clock
(26MHz)
RESET
Internal LDO
DC/DC
Converter
Sleep Clock
(32.768kHz)
BOOT done
Oscillation
When starting up ,Requires 2.0 V or more
Operation start
Boot Started
LDO On
DC/DC On
→
Reset release after stabilization of VDDIO is required
After sleep clock detection, internal power supply is
Switched.
(Temporarily switch to sleep mode)
Should not be VBAT<VDDIO
Oscillation
