14
User's Guide
ADI-2 FS © RME
11. Technical Background
11.1 Noise level in DS / QS Mode
The outstanding signal to noise ratio of the ADI-2 FS can be verified even without expensive
test equipment, by using the record level meters of various software. When activating the DS
and QS mode, the displayed noise level will rise from -117 dB to -110 dB at 96 kHz, and –89 dB
at 192 kHz. This is not a failure. This kind of measurement measures the noise of the whole
frequency range, at 96 kHz from 0 Hz to 48 kHz (RMS unweighted), at 192 kHz even from 0 Hz
to 96 kHz.
When limiting the measured area to 22 kHz (audio bandpass, weighted) the value would be -
117 dB again. This can be verified even with RME's DIGICheck. Although a dBA weighted value
does not include such a strong bandwidth limitation as from an audio bandpass, the displayed
value of –108 dB is nearly identical to the one at 48 kHz.
The reason for this behaviour is the noise shaping technology of the analog to digital convert-
ers. They move all noise and distortion to the in-audible higher frequency range, above 24 kHz.
That’s how they achieve their outstanding performance and sonic clarity. Therefore the noise is
slightly increased in the ultrasound area. High-frequent noise has a high energy. Add the dou-
bled (quadrupled) bandwidth, and a wideband measurement will show a significant drop in
SNR, while the human ear will notice absolutely no change in the audible noise floor.
11.2 SteadyClock FS
RME’s SteadyClock technology guarantees an excellent performance in all clock modes. Its
highly efficient jitter suppression refreshes and cleans up any clock signal.
Usually a clock section consists of an analog PLL for external synchronization and several
quartz oscillators for internal synchronization. SteadyClock requires one quartz only, using a
frequency not equalling digital audio. Modern circuit designs like hi-speed digital synthesizer,
digital PLL, 1 GHz sample rate and analog filtering allow RME to realize a completely newly
developed clock technology, right within the FPGA at lowest costs. The clock's performance
exceeds even professional expectations. Despite its remarkable features, SteadyClock reacts
quite fast compared to other techniques. It locks in fractions of a second to the input signal,
follows even extreme varipitch changes with phase accuracy, and locks directly within a range
of 28 kHz up to 200 kHz.
The further improved SteadyClock FS technology offers even lower self-jitter, and uses a low
phase noise quartz with jitter in the range of femtoseconds. Thanks to the highly efficient jitter
suppression, the AD- and DA-conversion always operates on highest sonic level, being com-
pletely independent from the quality of the incoming clock signal.
SteadyClock has been originally developed to gain a stable and clean clock from the heavily
jittery MADI data signal (MADI includes around 80 ns of jitter). Using the input sources of the
ADI-2 FS, SPDIF, ADAT or AES, you'll most probably never experience such high jitter values.
But SteadyClock would handle these easily.
Содержание ADI-2 FS
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