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PCI and IDE Configuration
8 Bit I/O Recovery
The recovery time is the length of time, measured in
Time
CPU clocks, which the system will delay after the
completion of an input/output request. This delay
takes place because the CPU is operating so much
faster than the input/output bus that the CPU must be
delayed to allow for the completion of the I/O.
This item allows you to determine the recovery time
allowed for 8 bit I/O. Choices are from NA, 1 to 8 CPU
clocks.
16 Bit I/O Recovery
This item allows you to determine the recovery time
Time
allowed for 16 bit I/O. Choise are from NA, 1 to 4 CPU
clocks.
The Choice: Enabled, Disabled.
Memory Hole At
In order to improve performance, certain space in
15M-16M
memory can be reserved for ISA cards. This memory
must be mapped into the memory space below 16 MB.
Enabled
Memory hole supported
Disabled
Memory hole not supported
Passive Release
When Enabled, CPU to PCI bus accesses are allowed
during passive release. Otherwise, the arbiter only
accepts another PCI master access to local DRAM.
The Choice: Enabled, Disabled.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer
to support delay transactions cycles. Select Enabled to
support compliance with PCI specification version 2.1.
The Choice: Enabled, Disabled.
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