Hardware
•
Frequency range: 0.010 - 32.000 MHz, 1Hz Steps * Usable up to 34 MHz+
•
DDC Processor: Xilinx XC3S500E
•
PC Interface: Ethernet 100 base-T (UDP/TCP)
•
DDC Filters: 110 dB+ Alias Free Dynamic Range (Single DDC FPGA Code)
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Decimation Rate: Variable 40-6400 (increments of 4)
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Output Sample Rate: 12.5 KHz to 2.0 MHz ( 24 or 16 bits) 64 Mb/s max data rate
•
DDC Flatness: <0.2 dB
•
Analog to Digital Converter: 16 bits @ 80 MHz. SNR = 78.2 dB
•
MDS 500 Hz, Low Gain ADC Setting, Dither off, Preselector on @ 10 MHz : -128 dBm Typ
•
MDS 500 Hz, High Gain ADC Setting, Dither off, Preselector on @ 10 MHz : -129 dBm Typ
•
Input IP3 (All Spacings) : 34 dBm Typ.
•
Preselection: 9 Bandpass Filters, 1 Lowpass Filter, Bypass option
•
Attenuators: 0dB, 10dB, 20dB, 30dB
•
Memory for Real Captures: 65536 x 16 bits (RBW = 1.221 KHz min)
•
External Radio Control: Built in RS-232 port
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Debug Port: USB Serial Port
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Internal Speaker: IP Address and Port Announcement
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Dimensions: 9” x 1.5” x 7”
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Power: 5 volts DC @ 1.5 Ams. (
Radio will turn off above 5.4 volts
)
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I/Q Data RX Mute on Pin 9 of RS-232 connector (Active Low)
•
Connections: 3 x BNC (RF In, 10 MHz Reference In, Aux/RX2 BNC) , Aux Stereo Jack, Ether-
net, USB Setup (optional), RS-232, Power. AUX connections are for future upgrades.
6
Jan 2012
RFSPACE, Inc.
NetSDR Wideband Digital Radio User’s Guide
