R8C/18 Group, R8C/19 Group
10. Clock Generation Circuit
Rev.1.30
Apr 14, 2006
Page 68 of 233
REJ09B0222-0130
10.5
Oscillation Stop Detection Function
The oscillation stop detection function detects the stop of the main clock oscillation circuit. The
oscillation stop detection function can be enabled and disabled by bits OCD1 to OCD0 in the OCD
register.
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
When the main clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b (oscillation stop
detection function enabled), the system is placed in the following state if the main clock stops.
•
OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
•
OCD3 bit in OCD register = 1 (main clock stops)
•
CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
•
Oscillation stop detection interrupt request is generated.
10.5.1
How to Use Oscillation Stop Detection Function
•
The oscillation stop detection interrupt shares a vector with the voltage monitor 2 interrupt, and
the watchdog timer interrupt. When using the oscillation stop detection interrupt and watchdog
timer interrupt, the interrupt source needs to be determined. Table 10.6 lists Determining Interrupt
Source for Oscillation Stop Detection, Watchdog Timer, and Voltage Monitor 2 Interrupts.
•
When the main clock restarts after oscillation stop, switch the main clock to the clock source of
the CPU clock and peripheral functions by a program.
•
Figure 10.9 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator
to Main Clock.
•
To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0
(peripheral function clock does not stop in wait mode).
•
Since the oscillation stop detection function is a function for cases where the main clock is
stopped by an external cause, set bits OCD1 to OCD0 to 00b (oscillation stop detection function
disabled) when the main clock stops or is started by a program, (stop mode is selected or the
CM05 bit is changed).
•
This function cannot be used when the main clock frequency is 2 MHz or below. In this case, set
bits OCD1 to OCD0 to 00b (oscillation stop detection function disabled).
•
To use the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral
functions after detecting the oscillation stop, set the HRA01 bit in the HRA0 register to 0 (low-
speed on-chip oscillator selected) and bits OCD1 to OCD0 to 11b (oscillation stop detection
function enabled).
To use the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral
functions after detecting the oscillation stop, set the HRA01 bit to 1 (high-speed on-chip oscillator
selected) and bits OCD1 to OCD0 to 11b (oscillation stop detection function enabled).
Table 10.5
Specifications of Oscillation Stop Detection Function
Item
Specification
Oscillation stop detection enable clock
and frequency bandwidth
f(XIN)
≥
2 MHz
Enabled condition for oscillation stop
detection function
Set bits OCD1 to OCD0 to 11b (oscillation stop detection
function enabled).
Operation at oscillation stop detection
Oscillation stop detection interrupt is generated
