Renesas QB-RL78D1A2, Руководство пользователя

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QB-RL78D1A2 In-Circuit Emulator APPENDIX A
R20UT3110EJ0101 Rev.1.01 Page 37 of 41
Nov 28, 2014
- POR/LVD
POR/LVD function is emulated by FPGA and additional ICE Control chip. The ICE Control chip sense
the target VDD with its AD converter.
Following device is used:
ICE Control chip: V850ES/SG3
Figure A-3. POR/LVD Block diagram
- LCD Controller/Driver
LCD function is emulated by FPGA and additional LCD driver.
Following device is used:
LCD driver: RL78/D1A (R5F10DSL :same as the target device)
LCD function is emulated by following operation.
Register setting of LCD are accepted by LCD Controller in the FPGA. LCD CTL write to the LCD
register of R5F10DSL on IO board using parallel command interface between FPGA and R5F10DSL on
IO board. R5F10DSL on IO board contains original program that receive the command from FPGA
then write data to own register.
There is a time lag to output LCD waveform outputs after setting LCD’s SFR.
Clock cannot be stopped.
Figure A-4. LCD Block diagram