Renesas M3A-HS64, Руководство пользователя

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M3A-HS64G02 Functions
4.2.4 SH7264 Multiplex Pins Used on the M3A-HS64G02
Rev. 1.00 Apr 30, 2009 4-11
REJ11J0034-0100
4
Table 4.2.11 SH7264 Multiplex Pin Functions (IIC3)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
IIC3 SDA1 PECR0 PE3MD[1:0] = B'01 PE3/ SDA1 /IRQ3
SCL1 PECR0 PE2MD[1:0] = B'01 PE2/ SCL1 /IRQ2
SDA0 PECR0 PE1MD[2:0] = B'001 PE1/ SDA0 /IOIS16#/IRQ1/TCLKA/ADTRG#
SCL0 PECR0 PE0MD[1:0] = B'01 PE0/ SCL0 /AUDIO_CLK/IRQ0
Table4.2.12 SH7264 Multiplex Pin Functions (RCAN-TL1)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
CRx1 PJCR0 PJ3MD[1:0] = B'01 PJ3/ CRx1 /CRx0&CRx1/IRQ1 RCAN-
TL1 CTx1 PJCR0 PJ2MD[2:0] = B'001 PJ2/ CTx1 /CTx0&CTx1/CS2#/SCK0/LCD_M_DISP
CRx0 PJCR0 PJ1MD[2:0] = B'001 PJ1/ CRx0 /IERxD/IRQ0/RxD0
CTx0 PJCR0 PJ0MD[2:0] = B'001 PJ0/ CTx0 /IETxD/CS1#/TxD0/A0
Table 4.2.13 SH7264 Multiplex Pin Functions (IEB)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
IEB IERxD PJCR0 PJ1MD[2:0] = B'010 PJ1/CRx0/ IERxD /IRQ0/RxD0
IETxD PJCR0 PJ0MD[2:0] = B'010 PJ0/CTx0/ IETxD /CS1#/TxD0/A0
Table 4.2.14 SH7264 Multiplex Pin Functions (FLCTL)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
FLCTL NAF7 PDCR3 PD15MD[1:0] = B'01 PD15/ D15/NAF7 /PWM2H
NAF6 PDCR3 PD14MD[1:0] = B'01 PD14/ D14/NAF6 /PWM2G
NAF5 PDCR3 PD13MD[1:0] = B'01 PD13/ D13/NAF5 /PWM2F
NAF4 PDCR3 PD12MD[1:0] = B'01 PD12/ D12/NAF4 /PWM2E
NAF3 PDCR2 PD11MD[1:0] = B'01 PD11/ D11/NAF3 /PWM2D
NAF2 PDCR2 PD10MD[1:0] = B'01 PD10/ D10/NAF2 /PWM2C
NAF1 PDCR2 PD9MD[1:0] = B'01 PD9/ D9/NAF1 /PWM2B
NAF0 PDCR2 PD8MD[1:0] = B'01 PD8/ D8/NAF0 /PWM2A
FWE# PDCR1 PD7MD[1:0] = B'01 PD7/ D7/FWE# /PWM1H
FALE PDCR1 PD6MD[1:0] = B'01 PD6/ D6/FALE /PWM1G
FCLE PDCR1 PD5MD[1:0] = B'01 PD5/ D5/FCLE /PWM1F
FRE# PDCR1 PD4MD[1:0] = B'01 PD4/ D4/FRE# /PWM1E
FCE# PFCR2 PF10MD[2:0] = B'101 PF10/A24/SSIWS3/SSL00/TIOC3B/ FCE#
FRB PFCR2 PF9MD[2:0] = B'101 PF9/A23/SSISCK3/RSPCK0/TIOC3A/ FRB
Table 4.2.15 SH7264 Multiplex Pin Functions (SDHI)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
SDHI SD_CD PKCR1 PK7MD[1:0] = B'10 PK7/PWM1H/ SD_CD
SD_WP PKCR1 PK6MD[1:0] = B'10 PK6/PWM1G/ SD_WP
SD_D1 PKCR1 PK5MD[1:0] = B'10 PK5/PWM1F/ SD_D1
SD_D0 PKCR1 PK4MD[1:0] = B'10 PK4/PWM1E/ SD_D0
SD_CLK PKCR0 PK3MD[1:0] = B'10 PK3/PWM1D/ SD_CLK
SD_CMD PKCR0 PK2MD[1:0] = B'10 PK2/PWM1C/ SD_CMD
SD_D3 PKCR0 PK1MD[1:0] = B'10 PK1/PWM1B/ SD_D3
SD_D2 PKCR0 PK0MD[1:0] = B'10 PK0/PWM1A/ SD_D2