R31UH0015EU0101 Rev.1.01
Page 4
Apr 26, 2022
8A3xxxx 72QFN Evaluation Kit Manual
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SysDPLL Input (Optional)
– An SMA connector, J46, is provided to supply a local OCXO/TCXO reference as
an optional reference for System DPLL.
▪
Crystal
: A crystal of various frequencies must be present for board operations. A 3225 footprint is provided for
SMT crystals. For easy plug-in of a canned crystal, two through-holes are also available.
▪
EEPROM
– An SO-8 socket is provided to hold an EEPROM device of compatible package. EEROM is used to
store firmware and customer configuration data, if needed.
1.1 Board Power Supply
The board uses a 5V supply for its power supplies. When running the board, please set the bench power
supply at 5V/2A. The red jack (J1) is positive; the black jack (J2) is the ground.
Multiple LDOs are used to generate 3.3V, 2.5V, and 1.8V from the +5V supply.
1.2 Voltage Selection Jumpers
There are eight headers/jumpers to select different voltages for different functional blocks of the chip. Each
header has pin 1 and 3 labeled in silkscreen – jumping pin 1 and pin 2 will select 3.3V; jumping pin 2 and pin 3 will
select 2.5V; no jumper will have 1.8V. See the following example for JP4 and JP9 – JP4 will select 2.5V, JP9 will
select 3.3V.
Figure 3. Example of Voltage Jumpers
The following list shows which head/jumper is used to select what voltage:
▪ JP1 - VDDD
▪ JP2 - VDDA
▪ JP3 - VCC_GPIO_DC
▪ JP4 - VDDO_Q8_3_5
▪ JP5 - VDDO_Q2_4_11
▪ JP6 - VDDO_1_10_7
▪ JP7 - VDD_CLK0
▪ JP9 - VDDO_Q0_9_6
Note
: VDD_FOD voltage is selected by resistor R908 and R909. In order to prevent damage to the device, both
R908 and R909 should not be stuffed, in which case VDD_FOD = 1.8V.
