R31UH0015EU0101 Rev.1.01
Page 3
Apr 26, 2022
8A3xxxx 72QFN Evaluation Kit Manual
1. Board Design
The following diagram identifies the various components of the evaluation board: input and output SMA
connectors, power supply jacks, and some jumper settings necessary for the board operations. Detailed
descriptions are included below.
Figure 2. 8A3xxxx 72QFN Evaluation Board – Detailed
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Input SMA connectors
– There are five differential inputs labeled CLK0/nCLK0 - CLK4/nCLK4. Each input
clock can be configured differentially (LVDS, PECL 2.5V, and PECL 3.3V) or in single-ended format (CMOS).
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Output SMA connectors
– There are 12 outputs labeled as Q0/nQ0 - Q11/nQ11. Each output clock can be
configured differentially (LVDS, LVPECL, or user-defined amplitude) or in single-ended format (LVCMOS . in-
phase or out-of-phase).
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GPIO switch, LEDs, and Test points
– There are seven GPIOs available. Each GPIO can be set a “low” or
“high” level (if input) or displayed with an LED (if output). Some GPIOs are used to set the chip in a certain
working condition on power-up. For more information, see “Table 18. GPIO Pin Usage at Start-Up” in the
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USB connector
– A USB mini connector connects the evaluation board to a PC for GUI communications. No
power is consumed from the USB connector other than to power the FTDI USB device.
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VDDQx voltage selection jumpers
– Each output voltage can be individually supplied with 1.8V, 2.5V, or 3.3V.
These jumpers are used to select the voltage for the output voltages.
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Reset button
: A small button is used to reset the board.
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OSCI Input connector
– An SMA connector, J45, is provided to optionally supply a clock signal to overdrive
the crystal.
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OCXO/TCXO Reference (Optional)
– An OCXO/TCXO footprint, output at J82. It can be connected to J46
(below) as the reference for System DPLL.
