Realtek RTL8100, Руководство по программированию, Страница: 6 / 10

RTL8100
2001/12/10 Rev.1.0
6
2 Packet Reception
2.1 Architecture
The receive path of the RTL8100 is designed as a ring buffer. This ring buffer is a physical continuous memory structure. Data
coming from the line is first stored in a Receive FIFO in the chip, and then moved to the receive buffer when the early receive
threshold is met. The register CBA keeps the current address of the data moved to the buffer. CAPR is then a read pointer which
keeps the address of data that the driver had read. The receiving packet status is stored in front of the packet (packet header).
Initialization Block
n n-1 n-2
1
2
3
4
5
RBSTART
Rcv. Buffers
m-1 m m-2
. . . .
TSAD0
TSAD1 TSAD2 TSAD3
TASD0
TSAD1
Packet
n
Packet
2
Packet
1
. . . .
Packet
m
Packet
2
Packet
1
. . . .
. . . .
Xmit Buffers
CR [7 : 0 ]
RBSTART [31 : 0 ]
TSAD3 [31 : 0 ]
TSAD2 [31 : 0 ]
TSAD1 [31 : 0 ]
TSAD0 [31 : 0 ]
RCR [31 : 0 ]
TCR [31 : 0 ]
CAPR [15 : 0 ]
TSD0 [31 : 0 ]
TSD3 [31 : 0 ]
TSD2 [31 : 0 ]
TSD1 [31 : 0 ]
CAPR