RTL8100
2001/12/10
Rev.1.0
2
1 Packet Transmission
1.1 Architecture
The transmit path of the RTL8100 uses 4 descriptors, each descriptor with a fixed IO address offset. The 4 descriptors are used in
a round-robin fashion. As a descriptor is written, PCI operations start and move packets in the memory which the descriptor
specifies to the Transmit FIFO. The transmit FIFO is a 2k byte buffer in the chip which holds the data which will be moved to the
line (cable). Data in the Transmit FIFO starts to move to the line when the early transmit threshold is met. The early transmit
threshold is also specified in the descriptor.
1.2 Transmit Descriptors
A transmit descriptor consist of 2 registers, which are specified below.
Register 1: Transmit Start Address (TSAD0-3) register. The physical address of each packet (Note: the packet must be in a
continuous physical memory)
Register 2: Transmit Status (TSD0-3) register. A detailed description of this register is listed below.
Bit
R/W
Symbol
Description
31 R CRS
Carrier Sense Lost:
This bit is set to 1 when the carrier is lost during
transmission of a packet.
30 R TABT
Transmit Abort:
This bit is set to 1 if the transmission of a packet was
aborted. This bit is read only, writing to this bit is not affected.
29 R OWC
Out of Window Collision:
This bit is set to 1 if the RTL8100 encountered an
"out of window" collision during the transmission of a packet.
28 R CDH
CD Heart Beat:
The same as RTL8029(AS).
This bit is cleared in the 100Mbps mode.
27-24 R NCC3-0
Number of Collision Count:
Indicates the number of collisions
encountered during the transmission of a packet.
23-22 -
-
Reserved
21-16 R/W ERTXTH5-0
Early Tx Threshold:
Specifies the threshold level in the Tx FIFO to begin
the transmission. When the byte count of the data in the Tx FIFO reaches
this level, (or the FIFO contains at least one complete packet) the RTL8100
will transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in unit of 32 bytes.
This threshold must be avoided from exceeding 2K byte.
15 R TOK
Transmit OK:
Set to 1 indicates that the transmission of a packet was
completed successfully and no transmit underrun occurs.
14 R TUN
Transmit FIFO Underrun:
Set to 1 if the Tx FIFO was exhausted during
the transmission of a packet. The RTL8100 can re-transfer data if the Tx
FIFO underruns and can also transmit the packet to the wire successfully
even though the Tx FIFO underruns. That is, when TSD<TUN>=1,
TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).
13 R/W OWN
OWN:
The RTL8100 sets this bit to 1 when the Tx DMA operation of this
descriptor was completed. The driver must set this bit to 0 when the
Transmit Byte Count (bit0-12) is written. The default value is 1.
12-0 R/W SIZE
Descriptor Size:
The total size in bytes of the data in this descriptor. If the
packet length is more than 1792 byte (0700h), the Tx queue will be invalid,
i.e. the next descriptor will be written only after the OWN bit of that long
packet's descriptor has been set.