Raisecom RC801-60B-FV35 Series, Руководство пользователя

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Raisecom Technology Co., Ltd
15
4.3.1. Setup of Timeslot Dip-switch (SW1 to SW4)
Timeslot switches are SW1, SW2, SW3 and SW4.
“ √ ” indicates enable; “×” indicates disable
SW1 definition (default is all OFF)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit
SET Frame Status TS1 TS2 TS3 TS4 TS5 TS6 TS7
ON Fractional √ √ √ √ √ √ √
OFF Unframed × × × × × × ×
SW2 definition (default is all OFF)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit
SET TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15
ON √ √ √ √ √ √ √ √
OFF × × × × × × × ×
SW3 definition (default is all OFF)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit
SET TS16 TS17 TS18 TS19 TS20 TS21 TS22 TS23
ON √ √ √ √ √ √ √ √
OFF × × × × × × × ×
SW4 definition (default is all OFF)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit
SET TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31
ON √ √ √ √ √ √ √ √
OFF × × × × × × × ×
Notice:
When the SW1-1 is OFF (unframed mode) the TS1 to TS31 is invalid.
When the SW1-1 is ON( Fractional mode) the TS1 to TS31 bits are valid and can not
be all OFF. That is to say there must be some timeslot which is enabled.
4.3.2. Function Dip-switch (SW5)
In below table “ √ ” indicates enable; “×” indicates disable
Definition of SW5 (The 1
st
and 2
nd
bits are ON in default and others are OFF)
1
st
bit 2
nd
bit 3
rd
bit 4
th
bit 5
th
bit 6
th
bit 7
th
bit 8
th
bit
Set
Timing1 Timing2 TS_FLOW BET RX CLK LP1_EN LP2_EN LP_SEL