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32
the
DAVID-II
is sometimes called the “FDNR” because each of the legs
to ground simulates a Frequency-Dependent Negative Resistance.
Referring back to the classic L-C design, resistors in series with the
signal replace series inductors, and each of the active circuits to ground
replaces an inductor/capacitor series-resonant element.
Components in the left channel filter have fixed values. The resonant
frequency of each of the right channel legs is variable over a small range
so that the two channels may be precisely matched in amplitude and
phase response.
A great “cookbook,” with this and other filter circuits which might prove
valuable to the broadcaster, is the
Electronic Filter Design Handbook
by
Arthur B. Williams, published by McGraw-Hill. The reader is kindly
directed to this source for a more informed discussion of how the FDNR
circuit works than we could possibly muddle-through here.
IC20B buffers the output of the low-pass filter and includes gain, both to
compensate for the 6dB filter loss and to present the proper amplitude
to the digital synthesis circuitry. The signal level corresponding to 100%
modulation is +10dBu at the output of IC20B.
PILOT AND SUBCARRIER GENERATION
Clock
As previously described in the PWM discussion, IC8C is a crystal-
controlled oscillator at 1.216Mhz. IC8D buffers the clock, and IC7A,
the first binary divider, furnishes the 608kHz digital synthesis
sampling frequency.
Pilot Generation
IC6 is an up/down BCD counter clocked at the 608kHz sampling
frequency. 1-of-10 decoder IC11, OR gate IC10C, and binary divider
IC5A work together to keep IC6 continually counting from zero to 8,
back down to zero, etc. Counting logic is decoded by a 1-of-9 de-
multiplexer (IC14 and IC16C) which samples a resistor string with
sine-weighted values. This generates
one-half
a sinewave for each
counting cycle. IC7B reverses the DC polarity applied to the top of the
resistor string for
every-other
up/down count, forming the complete
19kHz pilot sinewave from 32 discrete steps. R20 introduces an offset
to compensate for any difference between the power supply rails and
can be adjusted to null the 38kHz second harmonic component. The
segmented Stereo Pilot is buffered by IC15A
Center-
Sampling
Analog switch IC16A is controlled directly by the 1.216MHz clock,
turning on for one-half of one clock period precisely at the
center
of
each stepped pilot waveform sample. This charges C19 to the sample
voltage value, which is held by buffer stage IC17A until the next center
sample is taken. Center-sampling eliminates integration of switching
noise which is concurrent with leading and trailing edges of the
waveform steps.
