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following:
• T o cause all outputs to be set to a logic 1 during reset, connect pin 1 to pin 2 on
JP1 of the breadboard card (See Drawing No. 52-0010-000 for location of JP1).
To cause all outputs to be set to a logic 0 during reset, connect pin 2 to pin 3 on
JP1.
NOTE
The 7064 breadboard module is shipped with no connections on JP1. The user must
configure JP1 to achieve consistent output port reset levels. J P 1 has no effect on
ports configured for input.
3.3.2 P o r t Configurations
The 7064 ports can be configured in three ways:
• C l o c k e d Inputs. The user supplies a clock signal that stores data in the port. A t
a later time, the port can be read from the VXIbus.
•
B u f f e r e d
Jnput. Data on the
input lines are
read when the port is read from the
VXlbus. N o clock signal is required.
• L a t c h e d Output with Readback, D a t a written to an output port through the
VXlbus is held on the data lines until another write changes the data.
3.3.3 P o r t Control
There are two lines that control the configuration of a port, 0/Ix! and LAT/BUFFx!,
where x is the associated port number (0 to 11):
• T h e 0/Ix! line:
Used to configure the port as an input or an output. When
the 0/Ix! line is held low, the port functions as an input.
When the 0/Ix! line is held high, the port functions as an
output.
• L AT / B U F F x ! line: U s e d to configure an input port as either a clocked input or
a buffered input. When the LAT/Buffx! line is held low,
the input port functions as a buffered input. W h e n the
LAT/Buffx! line is held high, the input port functions as an
clocked input. I f the port is configured as an output, this
3-2
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