Rabbit 6000 User’s Manual
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60
5.2 Dependencies
5.2.1 I/O Pins
There are three chip select pins, /CS0, /CS1, and /CS2; two read strobes, /OE0 and /OE1; and two write
strobes, /WE0 and /WE1. /CS3 is available to the internal SRAMs only and does not come out to a pin.
There are 16 dedicated data bus pins, D0 through D15, and 25 dedicated address pins, A0 through A23,
and /A0 to allow byte access to 16 bit devices.
If the SYSCFG pin is held high on startup, the Memory Bank 0 Control Register and Memory Bank 0 Low
Control Register are set to a particular value that maps to the internal SRAM. See Section 5.3.1 for more
details.
The drive strength and slew rate are selectable for the address and data bus pins and for the memory strobe
pins (except /CS1) via ADPCR, DBPCR, and CPCR. /CS1 has a fixed setting of 8 mA drive and fast slew.
Internal pullup and/or pulldown resistors are also selectable on the data bus.
5.2.2 Clocks
All memory operations are clocked by the processor clock.
5.2.3 Interrupts
When a write is attempted to a write-protected 64 KB or 4 KB block, a write-protection violation interrupt
is generated. The interrupt request is cleared when it is handled. The write-protection violation interrupt
vector is in the IIR at offset 0x090. It is always set to Priority 3.
When a stack-related write is attempted to a region outside that set by the stack limit registers, a stack limit
violation occurs. The interrupt request is cleared when it is handled. The stack limit violation interrupt vec-
tor is in the IIR at offset 0x1B0. It is always set to Priority 3.
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