Rabbit 6000 User’s Manual
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61
5.3 Operation
5.3.1 Internal RAM
There are two internal RAM devices in the Rabbit 6000. A 1 MB RAM is located on /CS3, /OE0, /WE0,
and a 32 KB battery-backed SRAM is located on /CS3, /OE1, /WE1. Both of them can be run at speeds up
to 200 MHz with no additional wait states.
The 1 MB RAM is a pipelined device, meaning that the DMA peripheral can access it between code
fetches and data read/writes, providing a significant performance improvement for applications that use
DMA such as networking. However, there are some restrictions in the use of the 1 MB RAM:
1. If the 32 kHz clock is not present, its performance will be halved. This will not be noticeable unless
DMA is also operational.
2. The data contents will only be preserved if the main clock is greater than 12 MHz.
The internal 32 KB SRAM is powered by the VBAT pin. Its contents will be preserved as long as 1.2 V is
kept on VBAT.
5.3.2 Memory Management Unit (MMU)
Code execution takes place in the 64 KB logical memory space, which is divided into four segments: root,
data, stack, and extended (XMEM). The root segment is always mapped starting at physical address
0x000000, but the other segments can be remapped to start at any physical 4 KB block boundary.
The data and stack segment mappings are set by writing to the appropriate register, as shown in Table 5-1.
The DATASEG and STACKSEG registers provide backwards compatibility to the Rabbit 2000 and 3000
processors; these registers map directly to DATASEGL and STACKSEGL, but the contents of
DATASEGH and STACKSEGH are set to zero.
Table 5-1. Memory Management Registers
Register
Segment
Size
Comments
DATASEG
Data
8 bits
Maps to DATASEGL;
DATASEGH set to 0x00
DATASEGL
Data
8 bits
—
DATASEGH
Data
4 bits
—
STACKSEG
Stack
8 bits
Maps to STACKSEGL;
STACKSEGH set to 0x00
STACKSEGL
Stack
8 bits
—
STACKSEGH
Stack
4 bits
—
XPC
XMEM
8 bits
Loaded via instructions
LD XPC,A
and
LD A,XPC
LXPC
XMEM
12 bits
Loaded via instructions:
LD LXPC,HL
and
LD HL,LXPC
Содержание 6000
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