Rabbit 6000 User’s Manual
digi.com
21
2.3.2 Main PLL
The main PLL is optimally tuned for a 25 MHz clock input and to produce a 400 MHz output, which can
be fed directly to the Flexible Interface Modules (FIMs), and is divided by two to 200 MHz for processor
and peripheral operation. Note that the main PLL can be bypassed if lower frequencies are desired.
The main PLL is enabled in GCDR, but is not selected as the main clock until enabled in MSCR. If the 32
kHz clock is present, then the switchover to the PLL output for the main clock will not occur until 200 µs
after the bit is enabled in MSCR to allow the PLL output to stabilize. The status of the main PLL (stable
output or not) can be read in bit 0 of MSSR.
The main PLL input clock is restricted to 20–200 MHz, and the output frequency range is limited to 300–
400 MHz. There are further restrictions on the internal frequency
The main PLL divider values are located in GCM0R and GCM1R. These should be set to a nonzero value
before enabling the PLL. Some suggested PLL settings are described in Table 2-3, chosen to match other
clock requirements in the design to allow clock sharing. If other PLL settings are desired, please contact
your sales representative at Digi International.
Note that if the PLL is enabled, restrictions may exist for the use of the spectrum spreader and clock dou-
bler. The following sections provide more details.
Table 2-3. Suggested PLL Modes
Input Clock
Main Clock
(max)
FIM Clock
(max)
GCM0R
Setting
GCM1R
Setting
20 MHz
150 MHz
300 MHz
xxx10000
xxxx0001
20 MHz
200 MHz
400 MHz
xxx10100
xxxx0001
25 MHz
150 MHz
300 MHz
xxx01100
xxxx0001
25 MHz
200 MHz
400 MHz
xxx10000
xxxx0001
48 MHz
156 MHz
312 MHz
xxx01101
xxxx0010
48 MHz
192 MHz
384 MHz
xxx10000
xxxx0010
Содержание 6000
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