136
Rabbit 3000 Microprocessor
The following table summarizes Timer A’s capabilities.
The control/status register for Timer A (TACSR) is laid out as shown in Table 11-3.
Bits 1–7—Read/write, terminal count reached on timers A1-A7. Reading this status regis-
ter clears any bits (bits 1-7) that are on. Writing to these bits enables the interrupts for the
corresponding timer.
Bit 0—Write, set to a "1" to enable the clock (perclk/2) for Timer A, set to "zero" to dis-
able the clock (perclk/2 in Figure 11-1). Bits 1-7 are written (write only) to enable the
interrupt for the corresponding timer.
Table 11-2. Timer A Capabilities
Timer
Cascade
Interrupt
Dedicated connection
A1
none
yes
Parallel Ports D-G, Timer B
A2
from A1
yes
Serial Port E
A3
from A1
yes
Serial Port F
A4
from A1
yes
Serial Port A
A5
from A1
yes
Serial Port B
A6
from A1
yes
Serial Port C
A7
from A1
yes
Serial Port D
A8
none
no
Input Capture
A9
none
no
Pulse Width Modulator
A10
none
no
Quadrature Decoder
Table 11-3. Timer A Control and Status Register (adr = 0A0h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
A7 count
done
A6 count
done
A5 count
done
A4 count
done
A3 count
done
A2 count
done
A1 count
done
This bit is
write
only.
Write
A7
interrupt
enable
A6
interrupt
enable
A5
interrupt
enable
A4
interrupt
enable
A3
interrupt
enable
A2
interrupt
enable
A1
interrupt
enable
1—enable
Timer A
main
clock
(pclk/2)
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