User’s Manual
77
7.5 Output Pins CLK, STATUS, /WDTOUT, /BUFEN
Certain output pins can have alternate assignments as specified in Table 7-4.
Table 7-4. Global Output Control Register (GOCR = 0x0E)
Bit(s)
Value
Description
7:6
00
CLK pin is driven with peripheral clock.
01
CLK pin is driven with peripheral clock divided by 2.
10
CLK pin is low.
11
CLK pin is high.
5:4
00
STATUS pin is active (low) during a first opcode byte fetch.
01
STATUS pin is active (low) during an interrupt acknowledge.
10
STATUS pin is low.
11
STATUS pin is high.
3
1
WDTOUTB pin is low (1 cycle minimum, 2 cycles maximum, of 32 kHz).
0
WDTOUTB pin follows watchdog function.
2
x
This bit is ignored.
1:0
00
/BUFEN pin is active (low) during external I/O cycles.
01
/BUFEN pin is active (low) during data memory accesses.
10
/BUFEN pin is low.
11
/BUFEN pin is high.
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