3
HARDWARE CONCEPT
Table 1:
Input Specifications.
Channels
8
Bin width (ps)
81
Input pulse high level (V)
Min
2.4
Max
5
Input pulse width (ns)
Min
4
Input pulse separation (ns)
Min
5.5
Input Impedance (Ω)
(LV)TTL
50/5000
Max event rates (Mevents/s)
1ch counting
10
8ch counting
25
8ch time tags
3
Software Delay (ns)
Min
-50
Max
50
Figure 3:
Hardware concept of the quTAU.
An ASIC converts the incoming signals into
time tags, which are then analyzed by an FPGA and transferred to a PC via USB2.0.
quTAU/quPSI Manual V4.0 Page 7
