UMTS/HSPA Module Series
UG96 Hardware Design
UG96_Hardware_Design 35 / 76
RESET_N
S3
Close to S3
TVS
Figure 17: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated as the following figure.
VBAT
RESTARTING
Module
Status
RESET_N
RUNNING
STATUS
RUNNING
OFF
>5s
V
IH
≥
1.3V
>3s
V
IL
≤
0.5V
≥
100m
s
Figure 18: Timing of Resetting Module
3.9. RTC Interface
The RTC (Real Time Clock) can be powered by an external capacitor through the pin VRTC when the
module is powered down and there is no power supply for the VBAT. If the voltage supply at VBAT is
disconnected, the RTC can be powered by the capacitor. The capacitance determines the duration of
buffering when no voltage is applied to UG96.
The capacitor is charged from the internal LDO of UG96 when there is power supply for the VBAT. A
serial 1K
Ω resistor has been placed on the application inside the module. It limits the input current of the
capacitor.