5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 23 / 83
8
W_DISABLE1#
*
DI
Airplane mode control.
Active LOW.
1.8/3.3 V power domain
9
USB_DM
AI,
AO
USB 2.0 differential data (-)
10
WWAN_LED#
*
OD
RF status indication LED
It is an open drain and
active LOW signal.
11
GND
Ground
12
Notch
Notch
13
Notch
Notch
14
Notch
Notch
15
Notch
Notch
16
Notch
Notch
17
Notch
Notch
18
Notch
Notch
19
Notch
Notch
20
PCM_CLK
*
IO
PCM data bit clock
1.8 V power domain
21
CONFIG_0
DO
Not connected internally
22
PCM_DIN
*
DI
PCM data input
1.8 V power domain
23
WAKE_ON_WAN#
*
OD
Wake up the host.
Open drain
Active LOW.
24
PCM_DOUT
*
DO
PCM data output
1.8 V power domain
25
DPR
DI
Dynamic power reduction.
High level by default.
1.8 V power domain
26
W_DISABLE2#
*
DI
GNSS disable control.
1.8/3.3 V power domain
Active LOW.
27
GND
Ground
28
PCM_SYNC
*
IO
PCM data frame sync
1.8 V power domain
29
USB_SS_TX_M
AO
USB 3.1 transmit (-)
30
USIM_RST
DO
(U)SIM card reset
1.8/3.0 V power domain
31
USB_SS_TX_P
AO
USB 3.1 transmit data (+)