Quectel QuecOpen BG952A-GL, Проектирование аппаратного обеспечения

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LPWA Module Series
BG952A-GL_QuecOpen_Hardware_Design 22 / 72
Can be configured
as GPIOs.
MAIN_TXD 35 DO
Main UART
transmit
V
OL
max = 0.36 V
V
OH
min = 1.44 V
MAIN_CTS 36 DO
DTE clear to send
signal from DCE
(Connect to DTE’s
CTS)
MAIN_RTS 37 DI
DTE request to
send signal from
DCE (Connect to
DTE’s RTS) V
IL
min = -0.2 V
V
IL
max = 0.54 V
V
IH
min = 1.26 V
V
IH
max = 2.0 V
MAIN_DCD 38 DO
Main UART data
carrier detect
V
OL
max = 0.36 V
V
OH
min = 1.44 V
MAIN_RI 39 DO
Main UART ring
indication
CLI UART Interfaces
Pin Name Pin No. I/O Description DC Characteristics Comment
CLI_RXD2 94 DI
CLI UART2
receive
V
IL
min = -0.2 V
V
IL
max = 0.54 V
V
IH
min = 1.26 V
V
IH
max = 2.0 V
1.8 V power
domain.
It is recommended
to reserve one set
of test points.
CLI_TXD2 94 DO
CLI UART2
transmit
V
OL
max = 0.36 V
V
OH
min = 1.44 V
CLI_TXD1 27 DO
CLI UART1
transmit
CLI_RXD1 28 DI
CLI UART1
receive
V
IL
min = -0.2 V
V
IL
max = 0.54 V
V
IH
min = 1.26 V
V
IH
max = 2.0 V
Debug UART Interfaces
Pin Name Pin No. I/O Description DC Characteristics Comment
DBG_RXD 22 DI
Debug UART
receive
V
IL
min = -0.2 V
V
IL
max = 0.54 V
V
IH
min = 1.26 V
V
IH
max = 2.0 V
1.8 V power
domain.
If unused, keep
these pins open.
Can be configured
as GPIOs.
DBG_TXD
23 DO
Debug UART
transmit V
OL
max = 0.36 V
V
OH
min = 1.44 V
ADC Interfaces
Pin Name Pin No. I/O Description DC Characteristics Comment