LPWA Module Series
BG952A-GL_QuecOpen_Hardware_Design
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1. ADC input voltage must not exceed 1.8 V.
2. Keep all RESERVED pins and unused pins unconnected.
3. GND pins should be connected to ground in the design.
4. On BG952A-GL, pin 27 (CLI_TXD1) and pin 28 (CLI_RXD1) are connected to pin 95 (CLI_TXD2) and
pin 94 (CLI_RXD2) respectively inside the module.
5. The LNA is integrated inside the module. It is not recommended to use an external LNA. It is strongly
recommended to keep GNSS_LNA_EN (pin 51) and VDD_RF (pin 99) unconnected.
3.3. Pin Description
The following tables show the pin definition, alternate functions and GPIO pull up/down resistance of the
module.
Table 4: Definition of I/O Parameters
Type
Description
AI
Analog Input
AO
Analog Output
AIO
Analog Input/Output
DI
Digital Input
DO
Digital Output
DIO
Digital Input/Output
PI
Power Input
PO
Power Output
PD
Pull down
PU
Pull up
NOTES
Содержание QuecOpen BG952A-GL
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