LTE Standard Module Series
EC200T Series Hardware Design
EC200T_Series_Hardware_Design 45 / 90
MAIN_RTS 65
DI
Main UART request to
send
MAIN_DTR 66
DI
Main UART data
terminal ready
MAIN_TXD
67
DO
Main UART transmit
MAIN_RXD
68
DI
Main UART receive
Table 14: Pin Definition of Debug UART Interface
Pin Name
Pin No.
I/O
Description
Comment
DBG_RXD
11
DI
Debug UART receive
1.8 V power domain.
If unused, keep it open.
DBG_TXD
12
DO
Debug UART transmit
The logic levels are described in the following table.
Table 15: Logic Levels of Digital I/O
Parameter
Min.
Max.
Unit
V
IL
-0.3
0.6
V
V
IH
1.2
2.0
V
V
OL
0 0.45
V
V
OH
1.35
1.8
V
The module provides a 1.8 V UART interface. A level translator should be used if the application is
equipped with a 3.3 V UART interface. A level translator TXS0108EPWR provided by
Texas Instruments
is recommended. The following figure shows a reference design.