LTE Module Series
BG96-NA Hardware Design
BG96-NA_Hardware_Design Confidential / Released 38 / 64
The logic levels are described in the following table.
Table 13:Logic Levels of Digital I/O
Parameter
Min.
Max.
Unit
V
IL
-0.3
0.6
V
V
IH
1.2
2.0
V
V
OL
0 0.45
V
V
OH
1.35
1.8
V
The module provides 1.8V UART interface. A level translator should be used if your application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instrument is
recommended. The following figure shows a reference design.
Figure 18: Reference Circuit with Translator Chip
Please visit http://www.ti.comformore information.
Another example with transistor translation circuit is shown as below. Thecircuitdesign of dotted line
section can refer to the circuitdesign of solid line section, in terms of both module input and output circuit
designs, but please pay attention to the direction of connection.