QDFLD25
‐
xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 15 -
Ultra DMA timing parameters
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
UI
Unlimited
interlock
time
0 - 0 - 0 - 0 - 0 -
t
AZ
Maximum time allowed for output drivers to
release (from being asserted or negated)
- 10 - 10 - 10 - 10 - 10
t
ZAH
Minimum delay time required for output
drivers to assert or negate (from released
state)
20 - 20 - 20 - 20 - 20 -
t
ZAD
0 - 0 - 0 - 0 - 0 -
t
ENV
Envelope time (from DMACK- to STOP and
HDMARDY- during data out burst initiation)
20 70 20 70 20 70 20 55 20 55
t
RFS
Ready-to-final-STROBE time (no STROBE
edges shall be sent this long after negation
of DMARDY-)
- 75 - 70 - 60 - 60 - 60
t
RP
Ready-to-pause time (time that recipient
shall wait to initiate pause after negating
DMARDY-)
160 - 125 - 100 - 100 - 100 -
t
IORDYZ
Pull-up time before allowing IORDY to be
released
- 20 - 20 - 20 - 20 - 20
t
ZIORDY
Minimum time device shall wait before
driving IORDY
0 - 0 - 0 - 0 - 0 -
t
ACK
Setup and hold times for DMACK- (before
assertion or negation)
20 - 20 - 20 - 20 - 20 -
t
SS
Time from STROBE edge to negation of
DMARQ or assertion of STOP (when
sender terminates a burst)
50 50 - 50 - 20 - 20 -