QDFLD25
‐
xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 8 -
29
DMACK DMA
Acknowledge
30
GND Ground
31
INTRQ Interrupt
Request
32
IOCS16
CS I/O 16-Bit
33
HAB[1]
Host Address Bit 1
34
PDIAG Passed
Diagnostic
35
HAB[0]
Host Address Bit 0
36
HAB[2]
Host Address Bit 2
37
CS0
Chip Select 0
38
CS1 Chip
Select
1
39
DASP Drive
Active
40
GND Ground
41 VCC
Supply
Voltage
42
VCC
Supply
Voltage
43 GND
Ground
44
2
NC
Not
Connected
In the 44-pin version, this pin is defined as KEY, according to the ATA standard.
NC = These pins are not connected internally.
Signal usage in PIO & Multiword DMA mode.
Signal usage in Ultra DMA mode.
3.3. Electrical Description
The Industrial 2.5” PATA (IDE) SSD is optimized for operation with hosts. Table 8 describes the signals of 44-pin IDE
interface.
Table 8: Signal Description
Pin No.
Signal Name
Type
Description
1
HRESET-
I
Host reset signal, High: Reset.
37
CS0-
I
Chip select CS0
38
CS1-
I
Chip select CS1
31
INTRQ
O
Host interrupt signal.
25
HIOR-
3
I
I/O read strobe signal.
HDMARDY-
4
DMA ready during Ultra DMA data in burst
HSTROBE
4
Data strobe during Ultra DMA data out burst
23
HIOW-
3
I
I/O write strobe signal.
STOP
4
Stop during Ultra DMA data bursts
32
IOCS16-
O
Asserted in 16-bit access.
27
IORDY
3
O
I/O Ready Signal
DDMARDY-
4
DMA ready during Ultra DMA data out burst
DSTROBE
4
Data strobe during Ultra DMA data in burst
18, 16, 14, 12,
10, 8, 6, 4, 3,
5, 7, 9, 11, 13,
15, 17
HDB[15:0] I/O
Host
data
bus
33, 35, 36
HAB[2:0]
I/O
Host Address bus
28 CSEL-
I
I
Master/Slave select signal (cable select signal).
Low: Device operates as a master, High: Device operates as a slave.
Switch used.
39
DASP-
I/O
Used as an input port to check in the master mode to see if the slave
is present or not, and as an output port to check in the slave mode to
see if the slave for the master is present or not.
