<Document ID>
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 0.11 — 25 January 2007
10 of 230
NXP Semiconductors
UOC-TOP-64 N1 series
Signal processor for CRT TV
Fig 2.
Block diagram of the “MONO-90” TV processor
V-
D
R
IV
E
EH
T
O
AM DE
MO
DU
LA
TO
R
V
ISION
IF/A
GC/
AFC
PLL DEMOD.
V
IDE
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P.
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OUN
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UP DE
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Y
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IDE
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IDE
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IDE
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RS
DECO
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PAL/
SECAM/NTSC
BASE-BAND
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H/V SYNC SEP.
H-OSC.
+ PLL
2
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LO
OP
H-SH
IFT
H-
D
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VE
RTICA
L
AG
COU
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VIFIN
H-
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RGB/
YP
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BRI
RO
GO
BO
BLKIN/VGUARD
RGB CONTROL
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S
D/
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XT
INSE
RT
CCC/
BLACK ADJ.
WH
ITE
-P. A
D
J.
CONTR/BRIGHTN
RGB MA
TRIX
H/
V
REF
Y
D
E
L
AY
AD
J.
SATURATION
CVBS2/
Y2
YSY
NC
IFVO
/SV
O
SO
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L
DE
EMPH
ASIS
B3/
BLACK-STRETCH
BCLIN
CLK
GE
NE
RAT
ION
I
2
C-BUS
//
/
//
/
//
//
//
CSO
CSI
H/
VD
ISPO
H/
VD
ISPI
CLKI
CLKO
IREFRGB
R/G/B
VD
S
INS.
CIRN
CORB
SDA/SCL
IREF
IREFO
CVBSREF
CVBS I
N
RESET
TMSE
L
P
-PROCESSOR / TELETEXT DECODER / OSD
AM
A
UDIO
SE
LE
CT
SCART/
CINCH
LS/SCART/
CINCH
L
L
S
AU
DIO
OU
TPU
T
VO
LU
ME/
AV
L
SA
T
CONTROL
IN
P
B
-3
FM
SO
UN
D-D
O
W
N
-
MIXER
SW
IT
C
H
-OU
T
SECAM
PEAKING
R3/
G3
/
P
R
-3/
Y-
3
C2/
C3/
C
4
CVBS3/
Y3
C2/C3/C4/
CVBS4/Y4
I/O
s
A
VL/
SS
IF
OU
T/
F
M
DEMOUT
AVL
COR
ING
GAM
M
A
C
O
NTROL
