QEI ePAQ-9410, Руководство пользователя

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EPAQ-9410 Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 3
Table of Contents
1 Introduction ................................................................................................................. 7
2 References ................................................................................................................... 7
3 Blocks ......................................................................................................................... 7
3.1 Processor .............................................................................................................. 7
3.1.1 Memory Map ................................................................................................ 7
3.1.2 CPU GPIO Signal Usage .............................................................................. 7
3.1.3 Boot modes ................................................................................................... 9
3.2 Boot Modes .......................................................................................................... 9
3.2.1 CAPTURE and COMPARE ....................................................................... 10
3.2.2 GPIO_BIT_BANG_OUT_CH[0,1] ............................................................ 10
3.3 SDRAM .............................................................................................................. 11
3.4 NOR Flash .......................................................................................................... 11
3.5 NAND flash........................................................................................................ 11
3.6 SPI Flash ............................................................................................................ 12
3.7 Address Decoder CPLD ..................................................................................... 12
3.7.1 Heartbeat Register ....................................................................................... 13
3.7.2 L1 LED Register ......................................................................................... 13
3.7.3 L2 LED Register ......................................................................................... 14
3.7.4 L3 LED Register ......................................................................................... 14
3.7.5 L4 LED Register ......................................................................................... 14
3.7.6 SW10 High IP Address Register................................................................. 15
3.7.7 SW11 Low IP Address Register ................................................................. 15
3.7.8 Option DIP Switch Register........................................................................ 15
3.7.9 AD CPLD Revision Register ...................................................................... 16
3.8 QUAD UARTS .................................................................................................. 16
3.9 DUART .............................................................................................................. 17
3.10 Serial Routing CPLD ...................................................................................... 17
3.10.1 IRIG-B Bus Register ................................................................................... 18
3.10.2 IRIG_FIBER_TX Register ......................................................................... 18
3.10.3 IRIG-B_RS485_TXD Register ................................................................... 19
3.10.4 IRIG-B_OUTPUT_TO_MICRO Register .................................................. 20
3.10.5 IRIG-B_MOD_OUT_EN_H Register ........................................................ 20
3.10.6 CH8_RXD Register .................................................................................... 20
3.10.7 COM_EXP_IRIG-B Register .................................................................... 21
3.10.8 Telco [1,2] Mode Register .......................................................................... 21
3.10.9 Telco [1,2] Control Register ....................................................................... 22
3.10.10 RS232 Port [1,2] Mode Register ............................................................. 22
3.10.11 Bit-Bang CH [0,1] Register ..................................................................... 23
3.10.12 Bit-Bang [0,1] RTS# Control Register .................................................... 23
3.10.13 DUART [A,B] Register........................................................................... 24
3.10.14 SR CPLD Revision 0 Register ................................................................ 25
3.10.15 SR CPLD Revision 1 Register ................................................................ 25