EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 23
The table below summarizes supported values for RS232_MODE field.
Value
Description
0x0
RS232 port disabled
{CH[10,11]_TXD, CH[10,11]_RTS_L, CH[10,11]_TXCLK} =
{1'b1, 1'b1, 1'b0 };
0x1
RS232 port is controlled by a DUART channel, (RS232 port 1 is always controlled by
DUART CH A, RS232 port 2 is always controlled by CH B)
When an RS232 port is connected to the DUART channel, RTS# of the DUART is
connected to the RTS# of the RS232 port; TX clocks are "wired through".
{CH[10,11]_TXD, CH[10,11]_RTS_L, CH[10,11]_TXCLK } =
{DUART_CH[A,B]_TXD, DUART_CH[A,B]_RTS_L, CH[10,11]_TXCLK_OUT}
0x2
RS232 is controlled by a Bit-Bang channel, (RS232 port 1 is always controlled by the Bit-
Bang CH 0, RS232 port 2 is always controlled by the Bit-Bang CH 1)
{CH[10,11]_TXD, CH[10,11]_RTS_L, CH[10,11]_TXCLK} =
{BB[0,1]_TXD, BB[0,1]_RTS_L, 1'b0};
0x3-0xF
disabled
{CH[10,11]_TXD, CH[10,11]_RTS_L, CH[10,11]_TXCLK} =
{1'b1, 1'b1, 1'b0 };
3.10.11 Bit-Bang CH [0,1] Register
Register Name: BB[0,1]_SEL
Address: [0]: 0xB402_000E, [1]: 0xB402_000F
Access type: write-only
3
2
1
0
BB[0,1]_SEL
The BB[0,1]_SEL registers control the configuration of the Bit-Bang ports 0 and 1. The
Bit-Bang ports 0 and 1 are also known as CAPTURE_GPIO1_4 and
COMPARE_GPIO1_5.
The table below summarizes supported values for BB[0,1]_SEL field.
Value
Description
0x0
//disabled
BB[0,1]_RXD = 1'b1;
0x1
//driven by RS232 port 1
BB[0,1]_RXD = CH[10,11]_RXD;
0x2
//TELCO port routing
BB[0,1]_RXD = CH[14,15]_RXD;
0x3-0xF
//disabled, 0
BB[0,1]_RXD = 1'b0;
3.10.12 Bit-Bang [0,1] RTS# Control Register
Register Name: BB[0,1]_RTS_CTRL
Address: [0]: 0xB402_0010, [1]: 0xB402_0011
Access type: write-only
