QDI P6I440LX/DP, Руководство пользователя

Страница: 11 / 45

Chapter 2
2 - 3
Clear CMOS
Close Once
Normal
Clear CMOS
Note: You must shut down the power
supply first when you
want to clear the CMOS.
Memory Configuration
The P6I440LX/DP Legend IV mainboard supports up to four 168PIN 3.3V un-
buffered DIMM, provides a flexible size from 8MB up to 512MB SDRAM
memory or from 8MB up to 1GB EDO memory. The following set of rules
allows for optimum configurations.
Rules for populating a 440LX/DP Legend IV memory array:
DIMM sockets can be populated in any order. However, to take advantage of
potentially faster MA timing it is recommended to populate sockets in order.
SDRAM and EDO DIMMs can be mixed within the memory array.
The DRAM Timing register, which provides the DRAM speed grade
control for the entire memory array, must be programmed to use the
timings of the slowest DRAMs installed (Please refer to "Chipset
Features Setup" of BIOS).
Possible EDO DIMM memory size is 8MB, 16MB, 32MB, 64MB,
128MB, 256MB in each DIMM socket.
Possible SDRAM memory size is 8MB, 16MB, 32MB, 64MB, 128MB,
256MB in each DIMM socket.
Wide SCSI Selection
JP25 decides the on-board SCSI controller
whether to work in ultra wide SCSI mode or
ultra narrow SCSI mode. Please see the table
listed below.
JP15