BIOS Setup Information
RUBY-9712VG2A User’s Manual
4-12
This chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered
if data is being lost. Such a scenario might well occur if your system had mixed
speed DRAM chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.
DRAM Timing Selectable
This option provides DIMM plug-and-play support by serial presence detect (SPD)
mechanism via the system management bus (SMBUS) interface.
The choice: Manual, By SPD.
CAS Latency Time
This option controls the number of SCLKs between the time a read command is
sampled by the DRAMs and the time the GMCH samples correspondent data from
the DRAMs.
The choice: 2, 2.5, 3, Auto.
DRAM RAS# to CAS# Delay
This option controls the number of SCLKs (SDRAM Clock) from a row activate
command to a read or write command. If your system installs good quality of
SDRAM, you can set this option to “3 SCLKs” to obtain better memory performance.
Normally, the option will be set to Auto.
The choice: 2, 3, 4, and 5, Auto.
DRAM RAS# Precharge
This option controls the number of SCLKs for RAS# precharge. If your system
installs good quality of SDRAM, you can set this option to “3 SCLKs” to obtain
better memory performance. It is set to auto normally.
The choice: 2, 3, 4, and 5, Auto.
Precharge delay (tRAS)
The choice: 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15, Auto.
System Memory Frequency
Users are recommended to use Auto for memory frequency selection.
The choice: Auto, 333MHz, 400MHz.
