PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved
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3.10 JTAG Interface (JP7)
The PEX 8648 RDK base board includes a dedicated 2x5 JTAG header (JP7) to the PEX 8648 switch. (Refer to
Figure 19
.) The 10-pin connector is designed to allow a direct interface to third-party JTAG TAP Controllers,
such
as
the Corelis USB-1149.1/E Controller. The header provides connections for TCK, TDI, TDO, TMS, TRST#, and
GND.
There is no “standard” JTAG header pin arrangement; therefore, JTAG header type and pin assignments are
arbitrary. The header and pin assignment chosen for the PEX 8648 RDK base board is compatible with the
Corelis JTAG single TAP cable (AS00790050-A0).
Figure 19. JTAG Header (Top View)
3.11 I
2
C Interface (JP8 and JP9)
The PEX 8648 RDK base board includes a two-wire, I
2
C-compatible Slave mode interface, with 3-bit addressing.
Through this out-of-band Channel, users can read, write, and configure the PEX 8648 switch’s internal registers,
run internal output Probe mode, monitor Error Counters, and monitor other PEX 8648 switch statuses. The
PEX 8648 RDK base board provides two 2x2 pin headers (JP8 and JP9), which interface to the PEX 8648
switch’s I
2
C Port, to allow chaining of multiple boards.
There is no “standard” I
2
C header pin arrangement; therefore, I
2
C header type and pin assignments are arbitrary.
(Refer to
Figure 20
.) The lower three bits of the I
2
C Slave address selection is determined by a DIP switch setting
(SW4[3:1]).
Figure 20. I
2
C Headers (Top View)
