PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved
14
3.4 Reference
Clock
Circuitry
The differential PCI Express RefClk is brought onto the PEX 8648 RDK base board from the Host PC, by way of
the PEX 8648 RDK adapter board and a Serial ATA cable connection. It is used to drive a dual-level set of 1:4
Fan-Out buffers (U3, U4, U5, and U7) to provide a 1:12 Clock Fan-Out buffer. One of these clocks connects to the
PEX 8648 switch and is always enabled. The other 11 clocks connect to the 11 PCI Express slot connectors.
Except for Slot 5 and Slot 8, these RefClks are always enabled. Slot 5 is the downstream connection selected to
demonstrate Hot-Plug capability using the Parallel Hot-Plug interface. Therefore, by default, Slot 5 is enabled by
the PEX 8648 switch’s Parallel Hot-Plug Controller for Port 5. Slot 8 is the downstream connection selected to
demonstrate Hot-Plug capability using the Serial Hot-Plug Controller and an external I/O Expander IC.
Figure 15
illustrates the PEX 8648 RDK base board’s Reference Clock circuitry.
