Using PEX 8648 SMA Based (SI) Card White Paper – Version 1.3
© 2010 by PLX Technology, Inc. All Rights Reserved
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8.2 Analog Loopback (Single Card)
Configuration: Upstream Port = Port 0
This test loops the SMA output from Port 3 transmitter(s) to Port 3 receiver(s).
•
Analog Loopback (Cable) with UTP (on Port 3)
o
Enable External Loopback by EEPROM: Write
PHY Additional Status Register
254h[19:16]=8h in EEPROM. Power down system.
o
Wire the corresponding transmitter to receiver connections (either x1, x2 or x4)
o
Reboot the system.
o
Set
PHY User Pattern Register
210h through 21Ch with desired data pattern.
o
Enable Loopback Master: Set
Physical Layer Port Command Register
230h[12]. Verify
bit [15] is set.
o
Enable User Test Pattern: Set
Physical Layer Test Register
228h[31:28]=8h.
Now to check link status / errors;
o
Read
SerDes Quad 3 Diagnostic Data Register
244h. Verify User Test Pattern mode
active via bit [30]=0 (UTP checker)
o
Select desired SerDes (0 thru 3) for error checking via register 244h, bits [24:25] where 00
= SerDes channel 0.
o
Check error count for selected SerDes – bits [23:16] for UTP/PRBS error count. If link is
operating properly, value should be zero.
o
If more than one lane is connected, select alternate SerDes and check corresponding lane
errors per above.
Figure 6. Error Register
