PLX Technology PEX 8648 Скачать руководство пользователя страница 11

Using PEX 8648 SMA Based (SI) Card White Paper – Version 1.3 
© 2010 by PLX Technology, Inc. All Rights Reserved 

 

11 

8.1  Digital Loopback (Two Cards) 

  Step 1: Configuring port 3 on card #2 as the upstream port; 

o

  Plug card #2 in MB and boot the system. 

o

  Open PEX Device Editor (PDE) 

o

  Click on EEPROM editor. 

o

  Add register 0x1dc (default value should be 0x10200080) 

o

  Add register 1dc again and program the value 0x10200300 (port 3 is upstream port). 

 

 

o

 Shut 

down 

system. 

 

  Step 2 -Install Cards 

o

  Remove card #2 from MB. 

o

  Plug card #1 in MB. 

o

  Plug card #2 in slot provided on card #1. This will provide power and clock to card #2. 

o

  Connect card #1 Port 3 to card #2 Port 3 by SMA coax cables (note cables are equal 

length). Connect TX of card #1 to RX of card #2. Match Lane numbers. For x1, use Lane 
0, for x2 use Lane 0 and Lane 1. (You can add backplane in the path once you have 
verified that the initial setup works). 

  Digital Loopback Test 

o

 Reboot 

system. 

o

  Link between both cards should be up. You will see port 3 LED on the cards blink.  

o

  Launch PDE and using memory map put port 3 in loopback. The following registers are 

programmed on card #1 using memory map. 

ƒ

  Program registers 0x210-0x21C with any pattern. 

ƒ

  Set 0x230[12] to enable loopback on lanes 12-15. 

ƒ

  Check to see if loopback is established, 0x230[15] = 1. 

ƒ

  Set 0x228[31] to enable user pattern on lanes 12-15. 

ƒ

  Check 0x244 “SerDes quad 3 diagnostic data” for error count. This should be 

zero. 

ƒ

  Change pattern in register 0x210. 

ƒ

  Check 0x244. You should see error count. 

ƒ

  Reset bits 0x228[31], 0x254[19] and 0x230[12]. 

ƒ

 Reboot 

system 

 

Repeat test with backplane in path. Change SerDes settings and check for error counts. 

Содержание PEX 8648

Страница 1: ...EX 8648 SMA based SI Card White Paper Version 1 3 July 2010 Website www plxtech com Technical Support www plxtech com support Copyright 2008 by PLX Technology Inc All Rights Reserved Version 1 3 July...

Страница 2: ...ut adjust transmitter and receiver settings check Gen 1 Gen 2 link up thru a channel operate at a max x4 width check system errors run loopback and card to card signal integrity SI testing Figure 1 PL...

Страница 3: ...ception without the degradation of the PCIe connector The transmitter and receiver pairs of each lane of the port are clearly marked with lane and polarity however it is not necessary to track lane po...

Страница 4: ...urce of degraded signal performance If a clock other than the PCIe connector system clock is desired the PCB can be modified to accept an external differential clock via SMA J17 18 and relocation of z...

Страница 5: ...ister manipulation without an I2 C controller To move from signal observation to an adjustable PCIe link bin files are supplied which demonstrate how to convert the SMA port to the upstream link and o...

Страница 6: ...register 0234h Return bits 19 16 to 0 Terminated link is now in Gen 2 Compliance mode If it is desired to change the TX swing and emphasis settings it can be done as below without resetting the chip...

Страница 7: ...8 Data Book Table 19 11 setting of 19h o Receiver equalization left at default 0 o Signal Detection Threshold EIDLE set to minimum 0 for Port 3 only For RX equalization Port 3 SMA outputs is controlle...

Страница 8: ...Tools Select Find I2C Device 3 Locate and click I2C Scan button Type 68 for device address Next locate Select I2C Device Type and pull down 8648AB Next depress Find Devices You should see 8648AB appea...

Страница 9: ...er card or second device nearer the root complex by SMA coax cables note cables are equal length Connect TX to RX and RX to TX of the two devices Match lane numbers For x1 use Lane 0 For x2 use Lane 0...

Страница 10: ...both cards to see at least one reset in order to initiate link up negotiation If needed manually depress card reset switch 2 Two root complex systems each SI card is placed in a PC and the SMA ports...

Страница 11: ...d 1 to RX of card 2 Match Lane numbers For x1 use Lane 0 for x2 use Lane 0 and Lane 1 You can add backplane in the path once you have verified that the initial setup works Digital Loopback Test o Rebo...

Страница 12: ...Register 210h through 21Ch with desired data pattern o Enable Loopback Master Set Physical Layer Port Command Register 230h 12 Verify bit 15 is set o Enable User Test Pattern Set Physical Layer Test R...

Страница 13: ...s device as monitor either will work Now depress Open Monitor button o With Monitor screen now open select Port 3 Ingress and Port 3 Egress You can optionally deselect the Port 0 monitors Depress Star...

Страница 14: ...requires several writes to the base register in Station 0 Port 0 and a write to the Port 3 specific register As a point of clarity note that Port 3 consists of SerDes numbers 12 15 Port 3 Lane 0 3 Th...

Страница 15: ...low Figure 8 Example of Programming for Slave Loopback via EEPROM Note the above bin file is provided as part of the SI card documentation Using the PEX SDK this bin can be directly programmed into th...

Отзывы: