PLX Technology PEX 8648 Скачать руководство пользователя страница 10

Using PEX 8648 SMA Based (SI) Card White Paper – Version 1.3 
© 2010 by PLX Technology, Inc. All Rights Reserved 

 

10 

8  Using Two SI Cards for Link Testing 

Another means of testing employs the use of two SI cards. This approach can be used in three 
connectivity scenarios:  

1)  One root complex (PC) to control the PCIe link and one base card (i.e. PCIe compliance load 

board) to provide power to the downstream card. The default clocking for this configuration is 
asynchronous (hence PC clock must not set SSC active) or an out of band reference clock is fed 
into the downstream card. The downstream card is configured to have the SMA port as the 
Upstream. (

Note: it is necessary for both cards to see at least one reset in order to initiate link-up 

negotiation. If needed, manually depress card reset switch)

 

2)  Two root complex systems – each SI card is placed in a PC and the SMA ports connected. 

Typically, in this configuration, NT is employed to allow Host-to-Host connectivity. Standard 
clocking is again asynchronous. (

Note: it is necessary for both cards to see at least one reset in 

order to initiate link-up negotiation. If needed, manually depress card reset switch)

 

3)  One root complex, stacked connectivity – as shown below.  In this configuration, coherent 

clocking is maintained between cards. Consequently, the PC can have SSC enabled. If alternate 
reference clock injection is desired, it is done so by changing the RefClk input configuration on 
the bottom SI Card unit. Examples for this configuration are discussed. 

 

 

 

Figure 5. Single PC connectivity 

Содержание PEX 8648

Страница 1: ...EX 8648 SMA based SI Card White Paper Version 1 3 July 2010 Website www plxtech com Technical Support www plxtech com support Copyright 2008 by PLX Technology Inc All Rights Reserved Version 1 3 July...

Страница 2: ...ut adjust transmitter and receiver settings check Gen 1 Gen 2 link up thru a channel operate at a max x4 width check system errors run loopback and card to card signal integrity SI testing Figure 1 PL...

Страница 3: ...ception without the degradation of the PCIe connector The transmitter and receiver pairs of each lane of the port are clearly marked with lane and polarity however it is not necessary to track lane po...

Страница 4: ...urce of degraded signal performance If a clock other than the PCIe connector system clock is desired the PCB can be modified to accept an external differential clock via SMA J17 18 and relocation of z...

Страница 5: ...ister manipulation without an I2 C controller To move from signal observation to an adjustable PCIe link bin files are supplied which demonstrate how to convert the SMA port to the upstream link and o...

Страница 6: ...register 0234h Return bits 19 16 to 0 Terminated link is now in Gen 2 Compliance mode If it is desired to change the TX swing and emphasis settings it can be done as below without resetting the chip...

Страница 7: ...8 Data Book Table 19 11 setting of 19h o Receiver equalization left at default 0 o Signal Detection Threshold EIDLE set to minimum 0 for Port 3 only For RX equalization Port 3 SMA outputs is controlle...

Страница 8: ...Tools Select Find I2C Device 3 Locate and click I2C Scan button Type 68 for device address Next locate Select I2C Device Type and pull down 8648AB Next depress Find Devices You should see 8648AB appea...

Страница 9: ...er card or second device nearer the root complex by SMA coax cables note cables are equal length Connect TX to RX and RX to TX of the two devices Match lane numbers For x1 use Lane 0 For x2 use Lane 0...

Страница 10: ...both cards to see at least one reset in order to initiate link up negotiation If needed manually depress card reset switch 2 Two root complex systems each SI card is placed in a PC and the SMA ports...

Страница 11: ...d 1 to RX of card 2 Match Lane numbers For x1 use Lane 0 for x2 use Lane 0 and Lane 1 You can add backplane in the path once you have verified that the initial setup works Digital Loopback Test o Rebo...

Страница 12: ...Register 210h through 21Ch with desired data pattern o Enable Loopback Master Set Physical Layer Port Command Register 230h 12 Verify bit 15 is set o Enable User Test Pattern Set Physical Layer Test R...

Страница 13: ...s device as monitor either will work Now depress Open Monitor button o With Monitor screen now open select Port 3 Ingress and Port 3 Egress You can optionally deselect the Port 0 monitors Depress Star...

Страница 14: ...requires several writes to the base register in Station 0 Port 0 and a write to the Port 3 specific register As a point of clarity note that Port 3 consists of SerDes numbers 12 15 Port 3 Lane 0 3 Th...

Страница 15: ...low Figure 8 Example of Programming for Slave Loopback via EEPROM Note the above bin file is provided as part of the SI card documentation Using the PEX SDK this bin can be directly programmed into th...

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