XV-DVR9H
170
1
2
4
1
2
3
4
C
D
F
A
B
E
(1) Link relation
No.
Pin Name
I/O
Function
Active
18
LINKON
I
Link-on signal input
Clock input
When LPS is active, input 0.
−
17
LPS
O
Link power status output
Link power OFF : 0
Link power ON : 2.7 MHz pulse output (20 dividing of host clock 54 MHz)
−
16
LREQ
O
Link request output
−
15
SCLK
I
Clock input for Link control
LPS is active : 49.152 MHz input
LPS = 0 0 : fixed
−
12, 13
CTL [1 : 0]
I/O
PHY/Link control signal input/output
−
2-4, 6-8, 10,11 PHY_D [7 : 0]
I/O
Data input/output between PHY-Link
−
26-19
STREAM1 [7 : 0]
I/O
ISO data bus of stream interface 1
−
27
PACKETEN1
I/O
Packet enable signal input/output of stream interface 1
H/L
28
TSERROR1
I/O
Packet error signal input/output of stream interface 1
H/L
29
TSRW1
I/O
Data read/write enable signal input/output of stream interface 1
−
30
SYNC1
I/O
Frame synchronous signal input/output of stream interface 1
H/L
32
TSSUB1
I/O
Not used Connect to VDD or GND through a resistor.
H/L
47-40
STREAM2 [7 : 0]
I/O
ISO data bus of stream interface 2
−
33
PACKETEN2
I/O
Packet enable signal input/output of stream interface 2
H/L
34
TSERROR2
I/O
Packet error signal input/output of stream interface 2
H/L
36
TSRW2
I/O
Data read/write enable signal input/output of stream interface 2
−
37
SYNC2
I/O
Frame synchronous signal input/output of stream interface 2
H/L
38
TSSUB2
O
Not used Set to open.
−
(2) Video interface pins
No.
Pin Name
I/O
Function
Active
50
VCLKI
I
Video clock input (27 MHz)
−
51
VCLKO
O
Video clock output (27 MHz)
−
47-40
VD [7 : 0]
I/O
Video data signal
−
33
VSYNC
I/O
Video vertical sync. signal
L
34
HSYNC
I/O
Video horizontal sync. signal
L
Field index signal
−
PWM signal for video PLL
−
Pin Function
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