XV-DVR9H
165
5
7
8
5
6
7
8
C
D
F
A
B
E
UPD72852AGB-8EU (MAIN ASSY : IC5101)
• IEEE1394 Physical IC
Pin Arrangement
DGND
1
SCLK
2
IC (DL)
3
DV
DD
4
CTL0
5
CTL1
6
DGND
7
D0
8
D1
9
DV
DD
10
D2
11
D3
12
DGND
13
D4
14
D5
15
DGND
16
D6
17
D7
18
SUS/RES
19
DV
DD
20
DGND
21
XO
22
XI
23
A
GND
24
AV
DD
25
PC0
26
PC1
27
PC2
28
IC (AL)
29
CMC
3
0
AV
DD
31
CPS
32
48
TpBias1
47
AV
DD
46
TpA1p
45
TpA1n
44
TpB1p
43
TpB1n
42
AGND
41
TpBias0
40
AV
DD
39
TpA0p
38
TpA0n
37
TpB0p
36
TpB0n
35
AGND
34
RI1
33
AGND
64
DGND
63
LREQ
62
FNSel
61
SPD/BDB
60
D
V
DD
59
LPS
58
LK
ON
57
DGND
56
D
V
DD
55
RESETB
54
A
V
DD
53
A
G
ND
52
A
G
ND
51
IC (AL)
50
DIRECT
49
A
G
ND
Block Diagram
30
39
38
CMC
TpA0p
TpA0n
26
PC0
27
PC1
28
PC2
19
SUS/RES
63
LREQ
59
LPS
50
DIRECT
2
SCLK
58
32
LKON
Link
Interface
I/O
5
CTL0
6
CTL1
8
D0
9
D1
11
D2
12
D3
14
D4
15
D5
17
D6
18
D7
CPS
55
RESETB
Arbitration
and
Control State
Machine
Logic
Cable
Port 0
Receive Data
Decoder
and
Retimer
Voltage
and
Current
Generator
Crystal Oscillator
PLL System
and
Transmit Clock
Generator
Transmit Data
Encoder
Cable
Power
Status
37
36
TpB0p
TpB0n
46
45
TpA1p
TpA1n
Cable
Port 1
44
43
TpB1p
TpB1n
41 TpBias0
48 TpBias1
34 RI1
23 XI
22 XO
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TEL 13942296513 QQ 376315150 892498299