XV-DVR9H
169
5
7
8
5
6
7
8
C
D
F
A
B
E
Block Diagram
149
1
76
TXD
150
RXD
Host
Interface
<UART>
RESETB
202
HS_CLK
PHY_D [7 :
0]
CTL [1 :
0]
15
SCLK
16
LREQ
17
LPS
18
LINK
ON
STREAM [7 :
0]
TSR
W
PA
CKETEN
SYNC
TSSUB
VD [7 :
0]
VSYNC
HSYNC
FLD
117
CS
119
RWZ
120
IOR
47-40
12, 13
143-141, 139-132,
130-128, 126, 125
2-4, 6-8,
10, 11
175, 174, 172, 171,
169-167, 165-156
196, 194-189,
186-178
A [17 : 0]
D [15 : 0]
92, 90-83,
81-79
MA [11 : 0]
73-69, 66-64,
62-57, 55, 54
MD [15 : 0]
RDZ
System
Control
Test
Block
Host
Inteface
IEEE1394 Link Core
DV Codec Core
Exter
nal
Flash R
O
M
Interf
ace
SDRAM
Interf
ace
A
udio
Interf
ace
ace
Stream
Interface
16-bit Timer
Unit D
<TMD>
CPU Core
High-speed
Internal ROM
192 kbytes
151
SCS
147
SCK
145
SO
146
176
WRZ
177
104
103
102
101
SI
MRAS
EEPROM
Interface
<CSI>
High-speed
Internal ROM
60 kbytes
Memory
Controller
INTC
77 MCLK
75 MCAS
74 MWE
AMCLK44
AMCLK48
APWM
AMCLKO
97 PCM2
96 PCM1
98 AEMP1
93 ALRCK
94 ABCK
36 TSRW2 / FLD
33 PACKETEN2 / VSYNC
37 SYNC2
34 TSERROR2 / HSYNC
38 TSSUB2
29 TSRW1
27 PACKETEN1
30 SYNC1
28 TSERROR1
32 TSSUB1
50 VCLKI
51 VCLKO
STREAM2 [7 : 0] / VD [7 : 0]
26-19
STREAM1 [7 : 0]
53 VPWM
Selector
Selector
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