62
PDR-F10
IC7502(PDC066)
12pin: 2V
No
No
Yes
model check
IC7502(PDC066) 94 pin: 609/ System
IC7502(PDC066) 92 pin: Legato
IC7502(PDC066) 91 pin: High bit
RESET
It is an adjustment mode
by 3.5V or more.
The backup data is read from EEPROM
(Input selector and digital Volume etc.)
"POWER ON " display
Reset release of mechanism
control microcomputer (88 pin: "H")
Mechanism communication
Initialization of AD/DA Converter
Mechanism communication beginning
Setting of audio format
Mechanism communication
Input selection setting
Key reception
• EEPRO communication
IC7502(PDC066) 98 pin: EEP DATA
IC7502(PDC066) 100 pin: EEP CLOCK
• Mechanism communication
IC7502(PDC066) 7 pin: MACK (Output)
IC7502(PDC066) 28 pin: MREQ (Input)
IC7502(PDC066) 95 pin: MSI (Output)
IC7502(PDC066) 96 pin: MSO (Input)
IC7502(PDC066) 97 pin: MSCK (Input)
Operation mode usually
Terminal TEST check
IC7502(PDC066)
12pin: 3.5V
Yes
The unit checker mode
One second later
MAIN LOOP
At the operation usually
Power ON Sequence
7.1.2 TROUBLE SHOOTING
Содержание PDR-F10
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Страница 25: ...PDR F10 25 A B C D 5 6 7 8 5 6 7 8 A 1 5 CN302 NORMAL MECHA ADJ SYSTEM CONTROL 1 2 C ...
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Страница 76: ...76 PDR F10 AK8567 CD R CORE ASSY IC101 RF Processor Pin Function 1 2 ...
Страница 77: ...77 PDR F10 Pin Function 2 2 ...