MJ-D508
60
LR376487 (IC102: CORE MAIN UNIT ASSY)
Encode/Decode/ATRAC
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TOTMON
TEMON
SBCK
SBO
SBSY
SFSY
FOK
SENSE
COUT
MCCK
DINTX
VDD1
DGND
RSTX
SYD0
SYD1
SYD2
SYD3
SYD4
SYD5
SYD6
SYD7
SYWRX
SYRDX
SYRS
EFMO
PLCK
ACRCER
TCRS
RAD0
RAD1
RAWEX
RARASX
RAA9
RAD3
RAD2
RACASX
DGND
RAOEX
RAA8
RAA7
RAA6
RAA5
RAA4
VDD2
RAA10
RAA0
RAA1
RAA2
RAA3
FEMON
DADATA
ADDATA
DFCK
BCLK
LRCK
DGND
PLLBVC
DOUT
DIN
XO
XI
DGND
VDD1
VPO
VXI
CDBCLK
CDLRCK
CDDATA
TEST4
TEST3
TESO1
EXPORT1
EXPORT0
X700KO
EFMMON
AVCC
EFMI
AGND
AIN
EIN
TCG
BIN
FIN
VBAT
WBI
VDD1
DGND
TEST0
TEST1
TEST2
X176KO
FODRF
FODRR
TRDRF
TRDRR
SLDRF
SLDRR
SPDRF
SPDRR
LR376487
No.
Name
I/O
Description
1
∗
EFMMON
O
EFM monitor output
2
AVCC
–
Analog power supply
3
EFMI
I
EFM signal input from RF amp
4
AGND
–
Analog GND
5
AIN
I
Focus error signal A
6
EIN
I
Tracking error signal E
7
TCG
I
Track cross signal
8
BIN
I
Focus error signal B
9
FIN
I
Tracking error signal F
10
∗
VBAT
I
Power-supply voltage detection signal for
constant-voltage servo
11
WBI
I
ADIP wobble signal
12
VDD1
–
Digital power supply
13
DGND
–
Digital GND
14
TEST0
I
Test-use input;
normally connected to GND when used.
15
TEST1
I
16
TEST2
I
Test-use input; Encoder/Servo Mode and ATRAC
Mode changeover
No.
Name
I/O
Description
17
X176KO
O
Clock output; f = 176.4kHz (4fs)
18
FODRF
O
Focus servo forward output; PWM
19
FODRR
O
Focus servo reverse output; PWM
20
TRDRF
O
Tracking servo forward output; PWM
21
TRDRR
O
Tracking servo reverse output; PWM
22
SLDRF
O
Slide servo forward output; PWM
23
SLDRR
O
Slide servo reverse output; PWM
24
SPDRF
O
Spindle servo forward output or spindle servo
output; PWM
25
SPDRR
O
Spindle servo reverse output or spindle rotation
forward/reverse changeover
26
RAA3
O
Address output to external D-RAM; ADR3
27
RAA2
O
Address output to external D-RAM; ADR2
28
RAA1
O
Address output to external D-RAM; ADR1
29
RAA0
O
Address output to external D-RAM; ADR0 (LSB)
30
∗
RAA10
O
Address output to external D-RAM; ADR10 (MSB)
31
VDD2
–
Power supply for DRAM interface
Pin Assignment (Top view)
Pin Function
Содержание MJ-D508
Страница 20: ...MJ D508 20 A B C D 1 2 3 4 1 2 3 4 3 4 MAIN UNIT ASSY 2 2 C E CN701 13 14 16 15 12 17 ...
Страница 33: ...MJ D508 33 A B C D 5 6 7 8 5 6 7 8 Q304 POWER SUPPLY UNIT ASSY D MAIN UNIT ASSY C SIDE B ...
Страница 34: ...MJ D508 34 A B C D 1 2 3 4 1 2 3 4 DISPLAY UNIT ASSY E 4 4 DISPLAY UNIT ASSY ...
Страница 35: ...MJ D508 35 A B C D 5 6 7 8 5 6 7 8 C CN404 SIDE A SIDE B RNP1732 C ...
Страница 62: ...MJ D508 62 PDG240A IC701 DISPLAY UNIT ASSY System Control µ com Block Diagram Pin Assignment Top view ...
Страница 67: ...MJ D508 67 ...